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AXI4 Stream Demo: bugfix + datawith change
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Change the datawidth used for the CoreAXI4DMAController in
the AXI4Stream demo example to be 64'b from 32'b. This change allows the
CoreAXI4DMAController to transfer data at a higher maximum rate.

Resolve a bug with the AXI Stream data generator module which was
incorrectly implementing the AXI4 Stream specification. See SAR #128874.

Corresponding updates to build script and BFM scripts as a result of
these changes.

Signed-off-by: Patrick Owens <[email protected]>
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@p-owens
p-owens committed May 8, 2023
1 parent 2dc7cc2 commit 2feb03f
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Showing 8 changed files with 162 additions and 143 deletions.
52 changes: 38 additions & 14 deletions ...pport/additional_configurations/AXI4_STREAM_DATA_GENERATOR/AXI4_STREAM_DATA_GENERATOR.tcl
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63 changes: 53 additions & 10 deletions ...t/additional_configurations/AXI4_STREAM_DATA_GENERATOR/AXI4_STREAM_DATA_GENERATOR_BFM.tcl
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23 changes: 10 additions & 13 deletions ...t/additional_configurations/AXI4_STREAM_DATA_GENERATOR/ICICLE_MSS_PFSOC_MSS_FIC0_user.bfm
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Expand Up @@ -16,16 +16,15 @@
#-----------------------------------------------------------

int streamDescAddr

int transSize
int patternCount
int transSizeBytes
int destOffset

int memDest
int memDest
int dataWidthBytes

memmap dmaCtrl 0x6001_0000
memmap SRAM 0x6800_0000 # memory address of SRAM
memmap fabricSRAM 0x6000_0000
memmap SRAM 0x6800_0000 # memory address of SRAM
memmap fabricSRAM 0x6000_0000

procedure main;
#-----------------------------------------------------------
Expand All @@ -36,35 +35,33 @@ print "MESSAGE: START Running BFM file 'ICICLE_MSS_PFSOC_MSS_FIC0_user.bfm'"
print "MESSAGE: to access FIC0"
print "-"

set destOffset 0x20
set destOffset 0x20
set streamDescAddr 0x6000_0000
set dataWidthBytes 0x8

# setting up the DMA controller and the SRAM

# configuration register
# 4'b1101 {Descriptor Valid, Destination Data Ready, Destination Operand}
write w SRAM 0x0000 0x0D

set transSize 1024;
set transSizeBytes transSize * 4
# the stream generator will transmit 64-bit data up to the value of patternCount
set patternCount 256;
set transSizeBytes patternCount * dataWidthBytes

# Byte Count register
write w SRAM 0x0004 transSizeBytes


# Memory destination for stream (SRAM)
set memDest fabricSRAM + destOffset
write w SRAM 0x0008 memDest


# Stream Descriptor Address 0 Register
write w dmaCtrl 0x0460 streamDescAddr


# Enable IRQs - Interrupt 0 mask register
write w dmaCtrl 0x0014 0x0F


#-----------------------------------------------------------
# END of BFM
#-----------------------------------------------------------
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18 changes: 13 additions & 5 deletions ...t/additional_configurations/AXI4_STREAM_DATA_GENERATOR/ICICLE_MSS_PFSOC_MSS_FIC3_user.bfm
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Expand Up @@ -24,16 +24,24 @@ print "-"
#write x <address> <address_increment> <32 bit data>
#read x <address> <address_increment>

int patternCount

int transSize
set transSize 1024
# the steam generator will transmit data with an incrementing pattern up to 256
set patternCount 256

# writing to the pattern count register
write w streamCtrl 0x0 patternCount
wait 100

# setting the transfer size
write w streamCtrl 0x0 transSize
wait 50
# starting the stream
write w streamCtrl 0x4 0x1

# allow the stream to run for 200 cycles
wait 200

# stopping the stream
write w streamCtrl 0x4 0x0

#-----------------------------------------------------------
# END of BFM
#-----------------------------------------------------------
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19 changes: 11 additions & 8 deletions script_support/hdl/AXI4_STREAM_DATA_GENERATOR/AXI4_STREAM_DATA_GENERATOR.v
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Expand Up @@ -57,18 +57,19 @@ input ACLK, RSTN, TREADY;

output [1:0] TDEST;
output [7:0] TID;
output [3:0] TKEEP;
output [3:0] TKEEP, TSTRB;
output TLAST, TVALID;
output [31:0] TSTRB, TDATA;
output [31:0] TDATA;

wire ENABLE_GEN;
wire ENABLE_FSM;
wire [31:0] TX_SIZE;
wire RESETN_INTERNAL;


AXI4_STREAM_DATA_GENERATOR_ABP_Reg TRANS_SIZE (
.pclk(PCLK),
.presetn(PRESETN),
.presetn(PRESETN & RESETN_INTERNAL),
.psel(PSEL),
.pwrite(PWRITE),
.pwdata(PWDATA),
Expand All @@ -77,20 +78,21 @@ output [31:0] TSTRB, TDATA;
.prdata(PRDATA),
.trans_size(TX_SIZE),
.paddr(PADDR),
.start(ENABLE_FSM)
.start(ENABLE_FSM),
.reset_generator(RESETN_INTERNAL)
);

AXI4_STREAM_DATA_GENERATOR_FSM FSM (
.clk(ACLK),
.rst_n(RSTN),
.rst_n(RSTN & RESETN_INTERNAL),
.start(ENABLE_FSM),
.ready(TREADY),
.en(ENABLE_GEN)
);

AXI4_STREAM_DATA_GENERATOR_gen generator (
.clk(ACLK),
.rst_n(RSTN),
.rst_n(RSTN & RESETN_INTERNAL),
.en(ENABLE_GEN),
.tdata(TDATA),
.tvalid(TVALID),
Expand All @@ -99,7 +101,8 @@ output [31:0] TSTRB, TDATA;
.tkeep(TKEEP),
.tstrb(TSTRB),
.tdest(TDEST),
.tid(TID)
.tid(TID),
.tready(TREADY)
);

endmodule
endmodule
8 changes: 7 additions & 1 deletion script_support/hdl/AXI4_STREAM_DATA_GENERATOR/AXI4_STREAM_DATA_GENERATOR_ABP_Reg.v
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Expand Up @@ -49,6 +49,7 @@ module AXI4_STREAM_DATA_GENERATOR_ABP_Reg(
input wire [31:0] paddr,
output wire pslverr,
output reg start,
output reg reset_generator,
output reg pready,
output reg [31:0] prdata,
output reg [31:0] trans_size
Expand All @@ -60,7 +61,8 @@ module AXI4_STREAM_DATA_GENERATOR_ABP_Reg(
prdata <= 32'b0;
pready <= 1'b0;
trans_size <= 32'b0;
start <= 1'b0;
start <= 1'b0;
reset_generator <= 1'b1;
end else if (psel && pwrite) begin
prdata <= 32'b0;
case (paddr[3:0])
Expand All @@ -72,6 +74,10 @@ module AXI4_STREAM_DATA_GENERATOR_ABP_Reg(
start <= pwdata[0];
pready <= 1'b1;
end
4'b1000: begin
reset_generator <= !pwdata[0];
pready <= 1'b1;
end
default: begin
pready <= 1'b1;
end
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58 changes: 0 additions & 58 deletions script_support/hdl/AXI4_STREAM_DATA_GENERATOR/AXI4_STREAM_DATA_GENERATOR_DFF.v
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64 changes: 30 additions & 34 deletions script_support/hdl/AXI4_STREAM_DATA_GENERATOR/AXI4_STREAM_DATA_GENERATOR_gen.v
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Expand Up @@ -47,63 +47,59 @@ module AXI4_STREAM_DATA_GENERATOR_gen (
input wire [31:0] trans_size,
output wire tlast,
output wire tvalid,
input wire tready,
output wire [1:0] tdest,
output wire [3:0] tkeep,
output wire [7:0] tid,
output wire [31:0] tstrb,
output wire [3:0] tstrb,
output wire [31:0] tdata
);

localparam
INC = 32'b1;
INC = 32'b 1;

localparam
TKEEP_WIDTH = 4,
TSTRB_WIDTH = 32;
TSTRB_WIDTH = 4;

reg tlast_ff;
reg tlast_ff,tvalid_ff;
reg en_reg;
reg [31:0] tdata_ff;
wire [31:0] transSize_inter;
wire [31:0] transSize_out;

AXI4_STREAM_DATA_GENERATOR_DFF #(.N(32)) flipFlop_one (
.clk(clk),
.rst_n(rst_n),
.in(trans_size),
.out(transSize_inter)
);
AXI4_STREAM_DATA_GENERATOR_DFF #(.N(32)) flipFlop_two (
.clk(clk),
.rst_n(rst_n),
.in(transSize_inter),
.out(transSize_out)
);
wire txn_done;

assign txn_done = tready & tvalid & tlast;

always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
tdata_ff <= 32'b0;
tdata_ff <= 32'b1;
tlast_ff <= 1'b0;
end else begin
if (en) begin
if (tdata_ff == transSize_out) begin
tdata_ff <= 32'b0;
tlast_ff <= 1'b1;
end else begin
tdata_ff <= tdata_ff + INC;
tlast_ff <= 1'b0;
end
tvalid_ff <= 1'b0;
en_reg <= 1'b0;
end else if ((en | en_reg) & ~txn_done) begin
en_reg <= 1'b1;
tvalid_ff <= 1'b1;
if(tready & tvalid)begin
tdata_ff <= tdata_ff + INC;
if (tdata_ff == trans_size-1)
tlast_ff <= 1'b1;
end
end
end else begin
tdata_ff <= 32'b1;
tlast_ff <= 1'b0;
tvalid_ff <= 1'b0;
en_reg <= 1'b0;
end

end

assign tdest = 2'b0;
assign tid = 8'b0;

assign tdata = tdata_ff;
assign tvalid = (| tdata_ff);
assign tvalid = tvalid_ff;
assign tlast = tlast_ff;
assign tkeep = {TKEEP_WIDTH{(!(trans_size == tdata_ff) & (| tdata_ff))}};
assign tstrb = {{(TSTRB_WIDTH - 4){1'b0}},{TKEEP_WIDTH{(!(trans_size == tdata_ff) & (| tdata_ff))}}};

assign tkeep = {TKEEP_WIDTH{1'b1}};
assign tstrb = {TSTRB_WIDTH{1'b1}};

endmodule

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