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Test failures in Vector Fixed-point Arithmetic Instructions #163

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ghost opened this issue Nov 3, 2022 · 1 comment
Open

Test failures in Vector Fixed-point Arithmetic Instructions #163

ghost opened this issue Nov 3, 2022 · 1 comment
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@ghost
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ghost commented Nov 3, 2022 •
edited by ghost
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Test failures in Vector Fixed-point Arithmetic Instructions

Last updated: November 21, 2022

Description:

Tests for the unit testing have been added and necessary environment changes have been made to run the tests on Spike and ARA. Following tests are found to be failing on the RTL. The tests can be verified by running on Spike using the usual Make targets in ara/apps (usingmake riscv_tests_spike)

In this issue, vector fixed-point arithmetic instructions related failure have been reported. Other tests are also available. Each of these combination is a test file in ara/apps/riscv-tests/isa/rv64uv/ and is also listed in its Makefrag.

vsaddu

Failing:

vsaddu.vi_LMUL1SEW16
vsaddu.vi_LMUL1SEW32
vsaddu.vi_LMUL1SEW64
vsaddu.vi_LMUL1SEW8
vsaddu.vi_LMUL2SEW16
vsaddu.vi_LMUL2SEW32
vsaddu.vi_LMUL2SEW64
vsaddu.vi_LMUL2SEW8
vsaddu.vi_LMUL4SEW16
vsaddu.vi_LMUL4SEW32
vsaddu.vi_LMUL4SEW64
vsaddu.vi_LMUL4SEW8
vsaddu.vi_LMUL8SEW16
vsaddu.vi_LMUL8SEW32
vsaddu.vi_LMUL8SEW64
vsaddu.vi_LMUL8SEW8
vsaddu.vv_LMUL1SEW16
vsaddu.vv_LMUL1SEW32
vsaddu.vv_LMUL1SEW64
vsaddu.vv_LMUL1SEW8
vsaddu.vv_LMUL2SEW16
vsaddu.vv_LMUL2SEW32
vsaddu.vv_LMUL2SEW64
vsaddu.vv_LMUL2SEW8
vsaddu.vv_LMUL4SEW16
vsaddu.vv_LMUL4SEW32
vsaddu.vv_LMUL4SEW64
vsaddu.vv_LMUL4SEW8
vsaddu.vv_LMUL8SEW16
vsaddu.vv_LMUL8SEW32
vsaddu.vv_LMUL8SEW64
vsaddu.vv_LMUL8SEW8
vsaddu.vx_LMUL1SEW16
vsaddu.vx_LMUL1SEW32
vsaddu.vx_LMUL1SEW64
vsaddu.vx_LMUL1SEW8
vsaddu.vx_LMUL2SEW16
vsaddu.vx_LMUL2SEW32
vsaddu.vx_LMUL2SEW64
vsaddu.vx_LMUL2SEW8
vsaddu.vx_LMUL4SEW16
vsaddu.vx_LMUL4SEW32
vsaddu.vx_LMUL4SEW64
vsaddu.vx_LMUL4SEW8
vsaddu.vx_LMUL8SEW16
vsaddu.vx_LMUL8SEW32
vsaddu.vx_LMUL8SEW64
vsaddu.vx_LMUL8SEW8

vsadd

Failing:

vsadd.vi_LMUL1SEW16
vsadd.vi_LMUL1SEW32
vsadd.vi_LMUL1SEW64
vsadd.vi_LMUL1SEW8
vsadd.vi_LMUL2SEW16
vsadd.vi_LMUL2SEW32
vsadd.vi_LMUL2SEW64
vsadd.vi_LMUL2SEW8
vsadd.vi_LMUL4SEW16
vsadd.vi_LMUL4SEW32
vsadd.vi_LMUL4SEW64
vsadd.vi_LMUL4SEW8
vsadd.vi_LMUL8SEW16
vsadd.vi_LMUL8SEW32
vsadd.vi_LMUL8SEW64
vsadd.vi_LMUL8SEW8
vsadd.vv_LMUL1SEW16
vsadd.vv_LMUL1SEW32
vsadd.vv_LMUL1SEW64
vsadd.vv_LMUL1SEW8
vsadd.vv_LMUL2SEW16
vsadd.vv_LMUL2SEW32
vsadd.vv_LMUL2SEW64
vsadd.vv_LMUL2SEW8
vsadd.vv_LMUL4SEW16
vsadd.vv_LMUL4SEW32
vsadd.vv_LMUL4SEW64
vsadd.vv_LMUL4SEW8
vsadd.vv_LMUL8SEW16
vsadd.vv_LMUL8SEW32
vsadd.vv_LMUL8SEW64
vsadd.vv_LMUL8SEW8
vsadd.vx_LMUL1SEW16
vsadd.vx_LMUL1SEW32
vsadd.vx_LMUL1SEW64
vsadd.vx_LMUL1SEW8
vsadd.vx_LMUL2SEW16
vsadd.vx_LMUL2SEW32
vsadd.vx_LMUL2SEW64
vsadd.vx_LMUL2SEW8
vsadd.vx_LMUL4SEW16
vsadd.vx_LMUL4SEW32
vsadd.vx_LMUL4SEW64
vsadd.vx_LMUL4SEW8
vsadd.vx_LMUL8SEW16
vsadd.vx_LMUL8SEW32
vsadd.vx_LMUL8SEW64
vsadd.vx_LMUL8SEW8

vssub

Failing:

vssub.vv_LMUL1SEW16
vssub.vv_LMUL1SEW32
vssub.vv_LMUL1SEW64
vssub.vv_LMUL1SEW8
vssub.vv_LMUL2SEW16
vssub.vv_LMUL2SEW32
vssub.vv_LMUL2SEW64
vssub.vv_LMUL2SEW8
vssub.vv_LMUL4SEW16
vssub.vv_LMUL4SEW32
vssub.vv_LMUL4SEW64
vssub.vv_LMUL4SEW8
vssub.vv_LMUL8SEW16
vssub.vv_LMUL8SEW32
vssub.vv_LMUL8SEW64
vssub.vv_LMUL8SEW8
vssub.vx_LMUL1SEW16
vssub.vx_LMUL1SEW32
vssub.vx_LMUL1SEW64
vssub.vx_LMUL1SEW8
vssub.vx_LMUL2SEW16
vssub.vx_LMUL2SEW32
vssub.vx_LMUL2SEW64
vssub.vx_LMUL2SEW8
vssub.vx_LMUL4SEW16
vssub.vx_LMUL4SEW32
vssub.vx_LMUL4SEW64
vssub.vx_LMUL4SEW8
vssub.vx_LMUL8SEW16
vssub.vx_LMUL8SEW32
vssub.vx_LMUL8SEW64
vssub.vx_LMUL8SEW8

vssubu

Failing:

vssubu.vv_LMUL1SEW16
vssubu.vv_LMUL1SEW32
vssubu.vv_LMUL1SEW64
vssubu.vv_LMUL1SEW8
vssubu.vv_LMUL2SEW16
vssubu.vv_LMUL2SEW32
vssubu.vv_LMUL2SEW64
vssubu.vv_LMUL2SEW8
vssubu.vv_LMUL4SEW16
vssubu.vv_LMUL4SEW32
vssubu.vv_LMUL4SEW64
vssubu.vv_LMUL4SEW8
vssubu.vv_LMUL8SEW16
vssubu.vv_LMUL8SEW32
vssubu.vv_LMUL8SEW64
vssubu.vv_LMUL8SEW8
vssubu.vx_LMUL1SEW16
vssubu.vx_LMUL1SEW32
vssubu.vx_LMUL1SEW64
vssubu.vx_LMUL1SEW8
vssubu.vx_LMUL2SEW16
vssubu.vx_LMUL2SEW32
vssubu.vx_LMUL2SEW64
vssubu.vx_LMUL2SEW8
vssubu.vx_LMUL4SEW16
vssubu.vx_LMUL4SEW32
vssubu.vx_LMUL4SEW64
vssubu.vx_LMUL4SEW8
vssubu.vx_LMUL8SEW16
vssubu.vx_LMUL8SEW32
vssubu.vx_LMUL8SEW64
vssubu.vx_LMUL8SEW8

vaadd

Failing:

vaadd.vv_LMUL1SEW16
vaadd.vv_LMUL1SEW32
vaadd.vv_LMUL1SEW64
vaadd.vv_LMUL1SEW8
vaadd.vv_LMUL2SEW16
vaadd.vv_LMUL2SEW32
vaadd.vv_LMUL2SEW64
vaadd.vv_LMUL2SEW8
vaadd.vv_LMUL4SEW16
vaadd.vv_LMUL4SEW32
vaadd.vv_LMUL4SEW64
vaadd.vv_LMUL4SEW8
vaadd.vv_LMUL8SEW16
vaadd.vv_LMUL8SEW32
vaadd.vv_LMUL8SEW64
vaadd.vv_LMUL8SEW8
vaadd.vx_LMUL1SEW16
vaadd.vx_LMUL1SEW32
vaadd.vx_LMUL1SEW64
vaadd.vx_LMUL1SEW8
vaadd.vx_LMUL2SEW16
vaadd.vx_LMUL2SEW32
vaadd.vx_LMUL2SEW64
vaadd.vx_LMUL2SEW8
vaadd.vx_LMUL4SEW16
vaadd.vx_LMUL4SEW32
vaadd.vx_LMUL4SEW64
vaadd.vx_LMUL4SEW8
vaadd.vx_LMUL8SEW16
vaadd.vx_LMUL8SEW32
vaadd.vx_LMUL8SEW64
vaadd.vx_LMUL8SEW8

vaaddu

Failing:

vaaddu.vv_LMUL1SEW16
vaaddu.vv_LMUL1SEW32
vaaddu.vv_LMUL1SEW64
vaaddu.vv_LMUL1SEW8
vaaddu.vv_LMUL2SEW16
vaaddu.vv_LMUL2SEW32
vaaddu.vv_LMUL2SEW64
vaaddu.vv_LMUL2SEW8
vaaddu.vv_LMUL4SEW16
vaaddu.vv_LMUL4SEW32
vaaddu.vv_LMUL4SEW64
vaaddu.vv_LMUL4SEW8
vaaddu.vv_LMUL8SEW16
vaaddu.vv_LMUL8SEW32
vaaddu.vv_LMUL8SEW64
vaaddu.vv_LMUL8SEW8
vaaddu.vx_LMUL1SEW16
vaaddu.vx_LMUL1SEW32
vaaddu.vx_LMUL1SEW64
vaaddu.vx_LMUL1SEW8
vaaddu.vx_LMUL2SEW16
vaaddu.vx_LMUL2SEW32
vaaddu.vx_LMUL2SEW64
vaaddu.vx_LMUL2SEW8
vaaddu.vx_LMUL4SEW16
vaaddu.vx_LMUL4SEW32
vaaddu.vx_LMUL4SEW64
vaaddu.vx_LMUL4SEW8
vaaddu.vx_LMUL8SEW16
vaaddu.vx_LMUL8SEW32
vaaddu.vx_LMUL8SEW64
vaaddu.vx_LMUL8SEW8

vasub

Failing:

vasub.vv_LMUL1SEW16
vasub.vv_LMUL1SEW32
vasub.vv_LMUL1SEW64
vasub.vv_LMUL1SEW8
vasub.vv_LMUL2SEW16
vasub.vv_LMUL2SEW32
vasub.vv_LMUL2SEW64
vasub.vv_LMUL2SEW8
vasub.vv_LMUL4SEW16
vasub.vv_LMUL4SEW32
vasub.vv_LMUL4SEW64
vasub.vv_LMUL4SEW8
vasub.vv_LMUL8SEW16
vasub.vv_LMUL8SEW32
vasub.vv_LMUL8SEW64
vasub.vv_LMUL8SEW8
vasub.vx_LMUL1SEW16
vasub.vx_LMUL1SEW32
vasub.vx_LMUL1SEW64
vasub.vx_LMUL1SEW8
vasub.vx_LMUL2SEW16
vasub.vx_LMUL2SEW32
vasub.vx_LMUL2SEW64
vasub.vx_LMUL2SEW8
vasub.vx_LMUL4SEW16
vasub.vx_LMUL4SEW32
vasub.vx_LMUL4SEW64
vasub.vx_LMUL4SEW8
vasub.vx_LMUL8SEW16
vasub.vx_LMUL8SEW32
vasub.vx_LMUL8SEW64
vasub.vx_LMUL8SEW8

vasubu

Failing:

vasubu.vv_LMUL1SEW16
vasubu.vv_LMUL1SEW32
vasubu.vv_LMUL1SEW64
vasubu.vv_LMUL1SEW8
vasubu.vv_LMUL2SEW16
vasubu.vv_LMUL2SEW32
vasubu.vv_LMUL2SEW64
vasubu.vv_LMUL2SEW8
vasubu.vv_LMUL4SEW16
vasubu.vv_LMUL4SEW32
vasubu.vv_LMUL4SEW64
vasubu.vv_LMUL4SEW8
vasubu.vv_LMUL8SEW16
vasubu.vv_LMUL8SEW32
vasubu.vv_LMUL8SEW64
vasubu.vv_LMUL8SEW8
vasubu.vx_LMUL1SEW16
vasubu.vx_LMUL1SEW32
vasubu.vx_LMUL1SEW64
vasubu.vx_LMUL1SEW8
vasubu.vx_LMUL2SEW16
vasubu.vx_LMUL2SEW32
vasubu.vx_LMUL2SEW64
vasubu.vx_LMUL2SEW8
vasubu.vx_LMUL4SEW16
vasubu.vx_LMUL4SEW32
vasubu.vx_LMUL4SEW64
vasubu.vx_LMUL4SEW8
vasubu.vx_LMUL8SEW16
vasubu.vx_LMUL8SEW32
vasubu.vx_LMUL8SEW64
vasubu.vx_LMUL8SEW8

vssrl

Failing:

vssrl.vi_LMUL1SEW16
vssrl.vi_LMUL1SEW32
vssrl.vi_LMUL1SEW64
vssrl.vi_LMUL1SEW8
vssrl.vi_LMUL2SEW16
vssrl.vi_LMUL2SEW32
vssrl.vi_LMUL2SEW64
vssrl.vi_LMUL2SEW8
vssrl.vi_LMUL4SEW16
vssrl.vi_LMUL4SEW32
vssrl.vi_LMUL4SEW64
vssrl.vi_LMUL4SEW8
vssrl.vi_LMUL8SEW16
vssrl.vi_LMUL8SEW32
vssrl.vi_LMUL8SEW64
vssrl.vi_LMUL8SEW8
vssrl.vv_LMUL1SEW16
vssrl.vv_LMUL1SEW32
vssrl.vv_LMUL1SEW64
vssrl.vv_LMUL1SEW8
vssrl.vv_LMUL2SEW16
vssrl.vv_LMUL2SEW32
vssrl.vv_LMUL2SEW64
vssrl.vv_LMUL2SEW8
vssrl.vv_LMUL4SEW16
vssrl.vv_LMUL4SEW32
vssrl.vv_LMUL4SEW64
vssrl.vv_LMUL4SEW8
vssrl.vv_LMUL8SEW16
vssrl.vv_LMUL8SEW32
vssrl.vv_LMUL8SEW64
vssrl.vv_LMUL8SEW8
vssrl.vx_LMUL1SEW16
vssrl.vx_LMUL1SEW32
vssrl.vx_LMUL1SEW64
vssrl.vx_LMUL1SEW8
vssrl.vx_LMUL2SEW16
vssrl.vx_LMUL2SEW32
vssrl.vx_LMUL2SEW64
vssrl.vx_LMUL2SEW8
vssrl.vx_LMUL4SEW16
vssrl.vx_LMUL4SEW32
vssrl.vx_LMUL4SEW64
vssrl.vx_LMUL4SEW8
vssrl.vx_LMUL8SEW16
vssrl.vx_LMUL8SEW32
vssrl.vx_LMUL8SEW64
vssrl.vx_LMUL8SEW8

vssra

Failing:

vssra.vi_LMUL1SEW16
vssra.vi_LMUL1SEW32
vssra.vi_LMUL1SEW64
vssra.vi_LMUL1SEW8
vssra.vi_LMUL2SEW16
vssra.vi_LMUL2SEW32
vssra.vi_LMUL2SEW64
vssra.vi_LMUL2SEW8
vssra.vi_LMUL4SEW16
vssra.vi_LMUL4SEW32
vssra.vi_LMUL4SEW64
vssra.vi_LMUL4SEW8
vssra.vi_LMUL8SEW16
vssra.vi_LMUL8SEW32
vssra.vi_LMUL8SEW64
vssra.vi_LMUL8SEW8
vssra.vv_LMUL1SEW16
vssra.vv_LMUL1SEW32
vssra.vv_LMUL1SEW64
vssra.vv_LMUL1SEW8
vssra.vv_LMUL2SEW16
vssra.vv_LMUL2SEW32
vssra.vv_LMUL2SEW64
vssra.vv_LMUL2SEW8
vssra.vv_LMUL4SEW16
vssra.vv_LMUL4SEW32
vssra.vv_LMUL4SEW64
vssra.vv_LMUL4SEW8
vssra.vv_LMUL8SEW16
vssra.vv_LMUL8SEW32
vssra.vv_LMUL8SEW64
vssra.vv_LMUL8SEW8
vssra.vx_LMUL1SEW16
vssra.vx_LMUL1SEW32
vssra.vx_LMUL1SEW64
vssra.vx_LMUL1SEW8
vssra.vx_LMUL2SEW16
vssra.vx_LMUL2SEW32
vssra.vx_LMUL2SEW64
vssra.vx_LMUL2SEW8
vssra.vx_LMUL4SEW16
vssra.vx_LMUL4SEW32
vssra.vx_LMUL4SEW64
vssra.vx_LMUL4SEW8
vssra.vx_LMUL8SEW16
vssra.vx_LMUL8SEW32
vssra.vx_LMUL8SEW64
vssra.vx_LMUL8SEW8

vnclip

Failing:

vnclip.wi_LMUL1SEW16
vnclip.wi_LMUL1SEW32
vnclip.wi_LMUL1SEW8
vnclip.wi_LMUL2SEW16
vnclip.wi_LMUL2SEW32
vnclip.wi_LMUL2SEW8
vnclip.wi_LMUL4SEW16
vnclip.wi_LMUL4SEW32
vnclip.wi_LMUL4SEW8
vnclip.wv_LMUL1SEW16
vnclip.wv_LMUL1SEW32
vnclip.wv_LMUL1SEW8
vnclip.wv_LMUL2SEW16
vnclip.wv_LMUL2SEW32
vnclip.wv_LMUL2SEW8
vnclip.wv_LMUL4SEW16
vnclip.wv_LMUL4SEW32
vnclip.wv_LMUL4SEW8
vnclip.wx_LMUL1SEW16
vnclip.wx_LMUL1SEW32
vnclip.wx_LMUL1SEW8
vnclip.wx_LMUL2SEW16
vnclip.wx_LMUL2SEW32
vnclip.wx_LMUL2SEW8
vnclip.wx_LMUL4SEW16
vnclip.wx_LMUL4SEW32
vnclip.wx_LMUL4SEW8

vnclipu

Failing:

vnclipu.wi_LMUL1SEW16
vnclipu.wi_LMUL1SEW32
vnclipu.wi_LMUL1SEW8
vnclipu.wi_LMUL2SEW16
vnclipu.wi_LMUL2SEW32
vnclipu.wi_LMUL2SEW8
vnclipu.wi_LMUL4SEW16
vnclipu.wi_LMUL4SEW32
vnclipu.wi_LMUL4SEW8
vnclipu.wv_LMUL1SEW16
vnclipu.wv_LMUL1SEW32
vnclipu.wv_LMUL1SEW8
vnclipu.wv_LMUL2SEW16
vnclipu.wv_LMUL2SEW32
vnclipu.wv_LMUL2SEW8
vnclipu.wv_LMUL4SEW16
vnclipu.wv_LMUL4SEW32
vnclipu.wv_LMUL4SEW8
vnclipu.wx_LMUL1SEW16
vnclipu.wx_LMUL1SEW32
vnclipu.wx_LMUL1SEW8
vnclipu.wx_LMUL2SEW16
vnclipu.wx_LMUL2SEW32
vnclipu.wx_LMUL2SEW8
vnclipu.wx_LMUL4SEW16
vnclipu.wx_LMUL4SEW32
vnclipu.wx_LMUL4SEW8

Verification branch: main_verif_10x

Steps to recreate this issue:

  1. git clone https://github.com/pulp-platform/ara.git
  2. git remote add test_repo "https://github.com/10x-Engineers/ara"
  3. git fetch test_repo
  4. git checkout main_verif_10x
  5. cd apps
  6. make riscv_tests
  7. cd ../hardware
  8. make simv app="name of individual ELF" or make riscv_tests_simv -j4 to run regression
@ghost
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ghost commented Nov 21, 2022

Issue updated with failing/hanging status of available tests.

@moimfeld moimfeld mentioned this issue May 22, 2023
Merged
3 tasks
@mp-17 mp-17 added the bug Something isn't working label Jun 15, 2024
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