Issue in vector single-width averaging add and subtract instructions: wrong results

[SoufSilence]

In vector single-width averaging add and subtract instructions, it seems that the code of vaadd, vasubu, and vasub give wrong results.

For vaadd:

ara/hardware/src/lane/simd_alu.sv

Lines 186 to 196 in a9d8ed5

	VAADD, VAADDU: if (FixPtSupport == FixedPointEnable) unique case (vew_i)
	EW8: for (int b = 0; b < 8; b++) begin
	automatic logic [ 8:0] sum = opa.w8 [b] + opb.w8 [b];
	unique case (vxrm)
	2'b00: r = sum[0];
	2'b01: r = &sum[1:0];
	2'b10: r = 1'b0;
	2'b11: r = !sum[1] & (sum[0]!=0);
	endcase
	res.w8[b] = (op_i == VAADDU) ? sum[8:1] + r : {sum[7], sum[7:1]} + r;
	end

I think code {sum[7], sum[7:1]} + r will not give correct results.
For example, if opa.w8 and opb.w8 equals to 0x80, the results is 0. However, I believe the real result should be 0x80.

For vasub and vasubu:

ara/hardware/src/lane/simd_alu.sv

Lines 322 to 332 in a9d8ed5

	VASUB, VASUBU: if (FixPtSupport == FixedPointEnable) unique case (vew_i)
	EW8: for (int b = 0; b < 8; b++) begin
	automatic logic [ 8:0] sub = opb.w8 [b] - opa.w8 [b];
	unique case (vxrm)
	2'b00: r = sub[0];
	2'b01: r = &sub[1:0];
	2'b10: r = 1'b0;
	2'b11: r = !sub[1] & (sub[0]!=0);
	endcase
	res.w8[b] = (op_i == VSSUBU) ? (sub[7:0] >> 1) + r : $signed(sub[7:0]) >>> 1 + r;
	end

I believe that right shift sub[7:0] by 1 bit won't give correct results.

Of course, maybe my understanding is not correct, if so, I hope you can point out my problem, thanks a lot!

[mp-17]

Hello @SoufSilence,

Sorry for the late reply; I was busy with other projects! :-)
I will get back to this asap, thanks for reporting!

Best,
Matteo