Try to modify the axi data width but failed

[hellcer]

In order to analyze the impact of interface bandwidth on the operating efficiency of ara, I modified the param 'AxiWideDataWidth' in the file 'ara_tb.v' from '64 * NrLanes / 2' to '64 * NrLanes * 2'. However, after the modification, the CPU threw an exception at a very early moment and the testbench ended.
The information given by tb is:

Compared with trace_hart, I found that the processor PC is running normally between 0x8000_0000-0x8000_0e4a. When it jumps out of the function <_out_char>, the pc is correct (0x80001116) but the wrong instr value is taken out, causing the processor to enter exception handling:

The correct instruction at 0x80001116 should be:

This error is so weird, I don't know if it's the memory loaded program or the bus or something. But I do need to modify the bandwidth from ara to L2. I wonder if there is a more reasonable method?