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Fix some occurrences of -Wshadow=local
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Signed-off-by: Brian Cain <[email protected]>
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androm3da committed Sep 28, 2023
1 parent 134e348 commit 89e6980
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Showing 2 changed files with 8 additions and 11 deletions.
9 changes: 3 additions & 6 deletions target/hexagon/op_helper.c
Original file line number Diff line number Diff line change
Expand Up @@ -132,10 +132,9 @@ void HELPER(gather_store)(CPUHexagonState *env, uint32_t addr, int slot)
void HELPER(commit_hvx_stores)(CPUHexagonState *env)
{
uintptr_t ra = GETPC();
int i;

/* Normal (possibly masked) vector store */
for (i = 0; i < VSTORES_MAX; i++) {
for (int i = 0; i < VSTORES_MAX; i++) {
if (env->vstore_pending[i]) {
env->vstore_pending[i] = 0;
target_ulong va = env->vstore[i].va;
Expand All @@ -162,7 +161,7 @@ void HELPER(commit_hvx_stores)(CPUHexagonState *env)
g_assert_not_reached();
}
} else {
for (i = 0; i < sizeof(MMVector); i++) {
for (int i = 0; i < sizeof(MMVector); i++) {
if (test_bit(i, env->vtcm_log.mask)) {
cpu_stb_data_ra(env, env->vtcm_log.va[i],
env->vtcm_log.data.ub[i], ra);
Expand Down Expand Up @@ -505,10 +504,8 @@ void HELPER(probe_pkt_scalar_store_s0)(CPUHexagonState *env, int args)
static void probe_hvx_stores(CPUHexagonState *env, int mmu_idx,
uintptr_t retaddr)
{
int i;

/* Normal (possibly masked) vector store */
for (i = 0; i < VSTORES_MAX; i++) {
for (int i = 0; i < VSTORES_MAX; i++) {
if (env->vstore_pending[i]) {
target_ulong va = env->vstore[i].va;
int size = env->vstore[i].size;
Expand Down
10 changes: 5 additions & 5 deletions target/hexagon/translate.c
Original file line number Diff line number Diff line change
Expand Up @@ -553,7 +553,7 @@ static void gen_start_packet(DisasContext *ctx)
/* Preload the predicated registers into get_result_gpr(ctx, i) */
if (ctx->need_commit &&
!bitmap_empty(ctx->predicated_regs, TOTAL_PER_THREAD_REGS)) {
int i = find_first_bit(ctx->predicated_regs, TOTAL_PER_THREAD_REGS);
i = find_first_bit(ctx->predicated_regs, TOTAL_PER_THREAD_REGS);
while (i < TOTAL_PER_THREAD_REGS) {
tcg_gen_mov_tl(get_result_gpr(ctx, i), hex_gpr[i]);
i = find_next_bit(ctx->predicated_regs, TOTAL_PER_THREAD_REGS,
Expand All @@ -566,7 +566,7 @@ static void gen_start_packet(DisasContext *ctx)
* Only endloop instructions conditionally write to pred registers
*/
if (ctx->need_commit && pkt->pkt_has_endloop) {
for (int i = 0; i < ctx->preg_log_idx; i++) {
for (i = 0; i < ctx->preg_log_idx; i++) {
int pred_num = ctx->preg_log[i];
ctx->new_pred_value[pred_num] = tcg_temp_new();
tcg_gen_mov_tl(ctx->new_pred_value[pred_num], hex_pred[pred_num]);
Expand All @@ -575,7 +575,7 @@ static void gen_start_packet(DisasContext *ctx)

/* Preload the predicated HVX registers into future_VRegs and tmp_VRegs */
if (!bitmap_empty(ctx->predicated_future_vregs, NUM_VREGS)) {
int i = find_first_bit(ctx->predicated_future_vregs, NUM_VREGS);
i = find_first_bit(ctx->predicated_future_vregs, NUM_VREGS);
while (i < NUM_VREGS) {
const intptr_t VdV_off =
ctx_future_vreg_off(ctx, i, 1, true);
Expand All @@ -588,7 +588,7 @@ static void gen_start_packet(DisasContext *ctx)
}
}
if (!bitmap_empty(ctx->predicated_tmp_vregs, NUM_VREGS)) {
int i = find_first_bit(ctx->predicated_tmp_vregs, NUM_VREGS);
i = find_first_bit(ctx->predicated_tmp_vregs, NUM_VREGS);
while (i < NUM_VREGS) {
const intptr_t VdV_off =
ctx_tmp_vreg_off(ctx, i, 1, true);
Expand Down Expand Up @@ -1228,7 +1228,7 @@ void hexagon_translate_init(void)
offsetof(CPUHexagonState, mem_log_stores[i].data64),
store_val64_names[i]);
}
for (int i = 0; i < VSTORES_MAX; i++) {
for (i = 0; i < VSTORES_MAX; i++) {
snprintf(vstore_addr_names[i], NAME_LEN, "vstore_addr_%d", i);
hex_vstore_addr[i] = tcg_global_mem_new(cpu_env,
offsetof(CPUHexagonState, vstore[i].va),
Expand Down

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