sim only for vdd=1.8V

rahulk29 · Sep 24, 2024 · 8a89b3e · 8a89b3e
1 parent f720172
commit 8a89b3e
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/src/blocks/sram/mod.rs b/src/blocks/sram/mod.rs
@@ -406,7 +406,7 @@ pub(crate) mod tests {
                     let short_str = if short { "short" } else { "long" };
                     let corners = ctx.corner_db();
                     let mut handles = Vec::new();
-                    for vdd in [1.8, 1.6, 2.0] {
+                    for vdd in [1.8] {
                         for corner in corners.corners() {
                             let corner = corner.clone();
                             let params = $params.clone();