A small 32-bit implementation of the RISC-V architecture
Highlights :
- 2-stage pipeline (fetch, execute)
- 2 AHB-lite master interfaces (Code & Data)
- lot of code is generated from a high level description
- written in verilog (using iverilog or Xilinx xvsim as simulator)
- RV32I ISA simulator available
Still under development in dedicated branches:
- RVC support
- interrupt support (with auto push/pop of registers, like for Cortex-M)
- debugger support
FPGA version available (Digilent ARTY board - Xilinx Artix7)
See http://rbarzic.github.io/nanorv32 for more information