SV: Enable another test

rems-project · Feb 14, 2025 · 429d017 · 429d017
1 parent 73d38f7
commit 429d017
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diff --git a/test/c/assign_rename_bug.sail b/test/c/assign_rename_bug.sail
@@ -10,6 +10,7 @@ $option -undefined_gen
 
 val sub_vec_int = {
   c: "sub_bits_int",
+  systemverilog: "sub_bits_int",
   _: "sub_vec_int"
 } : forall 'n. (bits('n), int) -> bits('n)
 

diff --git a/test/sv/run_tests.py b/test/sv/run_tests.py
@@ -16,7 +16,6 @@
 
 skip_tests = {
     'all_even_vector_length', # loops
-    'assign_rename_bug', # loops
     'for_shadow', # loops
     'loop_exception', # loops
     'read_write_ram', # memory