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Lean: add support for register definitions #894

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merged 24 commits into from
Jan 27, 2025

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@lfrenot lfrenot commented Jan 17, 2025

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@lfrenot lfrenot requested a review from javra January 17, 2025 15:32
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github-actions bot commented Jan 17, 2025

Test Results

   12 files  ±0     24 suites  ±0   0s ⏱️ ±0s
  751 tests +1    751 ✅ +1  0 💤 ±0  0 ❌ ±0 
2 495 runs  +1  2 495 ✅ +1  0 💤 ±0  0 ❌ ±0 

Results for commit 05ea73d. ± Comparison against base commit 0b14166.

♻️ This comment has been updated with latest results.

src/lib/state.ml Outdated
hardline;
string " get_";
idd;
colon;
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Space needed before the colon

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Fixed 👍

src/lib/state.ml Outdated
idd;
colon;
space;
string "SailM (";
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The brackets for the argument of SailM are not needed because whoever produces a composite term should be in charge of bracketing (in this case doc_typ).

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Fixed 👍


open Sail

class MonadReg where
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Shouldn't the register state be part of the state that's carried by SailM? That would give us the getter and setter "for free" instead? Or do we want to keep this flexible? What's your opinion on this, @bacam ?

@lfrenot lfrenot force-pushed the lean-register-clean branch from 290094b to 6840387 Compare January 21, 2025 11:05
| _ -> failwith ("Pattern " ^ string_of_pat_con pat ^ " " ^ string_of_pat pat ^ " not translatable yet.")

(* Copied from the Coq PP *)
let rebind_cast_pattern_vars pat typ exp =
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Does Lean actually need this? (It's to deal with a limitation of Coq's let-binding patterns.)

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Lean can pattern match in let-bindings if there's a single constructor, is that enough?

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That's roughly what Coq allows, except with the limitation that you can't have type annotations deep inside the pattern.

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Oh, now that I think about it, it may also have been to ensure that sufficient bitvector casts are inserted (e.g., when you have bits(8 * 'n) and need bits('n * 8).

| E_typ (typ, e) -> parens (separate space [doc_exp ctx e; colon; doc_typ ctx typ])
| E_typ (typ, e) -> (
match e with
| E_aux (E_assign _, _) -> doc_exp ctx e
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I might try and get rid of these silly unit type annotations on assignments when they're generated, as they affect several backends.

test/lean/registers.expected.lean Show resolved Hide resolved
@javra javra requested a review from bacam January 21, 2025 16:02
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javra commented Jan 23, 2025

Why not just make the RegisterType argument to PreSailM explicit, then you don't need the @ and the _ _

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lfrenot commented Jan 23, 2025

Why not just make the RegisterType argument to PreSailM explicit, then you don't need the @ and the _ _

@javra that would also be nice, but I'm not sure how make them explicit for PreSailM and implicit for the rest, while still using the variable

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javra commented Jan 23, 2025

abbrev PreSailM (RegisterType : Register → Type) :=
  EStateM Error (@SequentialSate Register RegisterType _ _)

I think it should also be explicit in SequentialState

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lfrenot commented Jan 23, 2025

@javra Thanks, I've done the edits

test/lean/bitfield.sail Outdated Show resolved Hide resolved
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bacam commented Jan 24, 2025

Looks good, but maybe some of the commented out code looks old, perhaps those bits should be removed?

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lfrenot commented Jan 27, 2025

Looks good, but maybe some of the commented out code looks old, perhaps those bits should be removed?

@bacam Yes, thanks for the notice. It should be good now.

@bacam bacam merged commit 68c1009 into rems-project:sail2 Jan 27, 2025
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3 participants