allow to spscify config parameters on register map (#41, rggen/rggen#221

)
rggen · Jan 21, 2025 · 3e9f006 · 3e9f006
1 parent 3b6f53e
commit 3e9f006
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Showing 16 changed files with 31 additions and 31 deletions.
diff --git a/lib/rggen/vhdl/register/type/external.rb b/lib/rggen/vhdl/register/type/external.rb
@@ -5,7 +5,7 @@
     build do
       generic :strobe_width, {
         name: "#{register.name}_STROBE_WIDTH".upcase,
-        type: :positive, default: configuration.bus_width / 8
+        type: :positive, default: register_block.byte_width
       }
       output :external_valid, {
         name: "o_#{register.name}_valid"

diff --git a/lib/rggen/vhdl/register_block/protocol.rb b/lib/rggen/vhdl/register_block/protocol.rb
@@ -30,7 +30,7 @@ def library_name
       end
 
       def bus_width
-        configuration.bus_width
+        register_block.bus_width
       end
 
       def local_address_width
@@ -47,8 +47,8 @@ def byte_size
     end
 
     factory do
-      def target_feature_key(configuration, _register_block)
-        configuration.protocol
+      def target_feature_key(_configuration, register_block)
+        register_block.protocol
       end
     end
   end

diff --git a/lib/rggen/vhdl/register_block/vhdl_top.rb b/lib/rggen/vhdl/register_block/vhdl_top.rb
@@ -59,7 +59,7 @@ def address_width
     end
 
     def bus_width
-      configuration.bus_width
+      register_block.bus_width
     end
 
     def value_width

diff --git a/spec/rggen/vhdl/bit_field/vhdl_top_spec.rb b/spec/rggen/vhdl/bit_field/vhdl_top_spec.rb
@@ -5,8 +5,8 @@
   include_context 'clean-up builder'
 
   before(:all) do
-    RgGen.enable(:global, [:bus_width, :address_width, :enable_wide_register, :library_name])
-    RgGen.enable(:register_block, [:name, :byte_size])
+    RgGen.enable(:global, [:address_width, :enable_wide_register, :library_name])
+    RgGen.enable(:register_block, [:name, :byte_size, :bus_width])
     RgGen.enable(:register_file, [:name, :offset_address, :size])
     RgGen.enable(:register, [:name, :offset_address, :size, :type])
     RgGen.enable(:bit_field, [:name, :bit_assignment, :type, :initial_value, :reference])

diff --git a/spec/rggen/vhdl/register/type/default_spec.rb b/spec/rggen/vhdl/register/type/default_spec.rb
@@ -5,8 +5,8 @@
   include_context 'vhdl common'
 
   before(:all) do
-    RgGen.enable(:global, [:bus_width, :address_width, :enable_wide_register, :library_name])
-    RgGen.enable(:register_block, :byte_size)
+    RgGen.enable(:global, [:address_width, :enable_wide_register, :library_name])
+    RgGen.enable(:register_block, [:byte_size, :bus_width])
     RgGen.enable(:register_file, [:name, :offset_address, :size])
     RgGen.enable(:register, [:name, :offset_address, :size, :type])
     RgGen.enable(:bit_field, [:name, :bit_assignment, :type, :initial_value, :reference])

diff --git a/spec/rggen/vhdl/register/type/external_spec.rb b/spec/rggen/vhdl/register/type/external_spec.rb
@@ -5,8 +5,8 @@
   include_context 'vhdl common'
 
   before(:all) do
-    RgGen.enable(:global, [:bus_width, :address_width, :enable_wide_register, :library_name])
-    RgGen.enable(:register_block, :byte_size)
+    RgGen.enable(:global, [:address_width, :enable_wide_register, :library_name])
+    RgGen.enable(:register_block, [:byte_size, :bus_width])
     RgGen.enable(:register, [:name, :type, :offset_address, :size])
     RgGen.enable(:register, :type, :external)
     RgGen.enable(:bit_field, :name)

diff --git a/spec/rggen/vhdl/register/type/indirect_spec.rb b/spec/rggen/vhdl/register/type/indirect_spec.rb
@@ -5,8 +5,8 @@
   include_context 'vhdl common'
 
   before(:all) do
-    RgGen.enable(:global, [:bus_width, :address_width, :enable_wide_register, :library_name])
-    RgGen.enable(:register_block, :byte_size)
+    RgGen.enable(:global, [:address_width, :enable_wide_register, :library_name])
+    RgGen.enable(:register_block, [:byte_size, :bus_width])
     RgGen.enable(:register_file, [:name, :offset_address, :size])
     RgGen.enable(:register, [:name, :offset_address, :size, :type])
     RgGen.enable(:register, :type, [:indirect])

diff --git a/spec/rggen/vhdl/register/type/rw_spec.rb b/spec/rggen/vhdl/register/type/rw_spec.rb
@@ -5,8 +5,8 @@
   include_context 'vhdl common'
 
   before(:all) do
-    RgGen.enable(:global, [:bus_width, :address_width, :enable_wide_register, :library_name])
-    RgGen.enable(:register_block, :byte_size)
+    RgGen.enable(:global, [:address_width, :enable_wide_register, :library_name])
+    RgGen.enable(:register_block, [:byte_size, :bus_width])
     RgGen.enable(:register_file, [:name, :offset_address, :size])
     RgGen.enable(:register, [:name, :offset_address, :size, :type])
     RgGen.enable(:register, :type, :rw)

diff --git a/spec/rggen/vhdl/register/vhdl_top_spec.rb b/spec/rggen/vhdl/register/vhdl_top_spec.rb
@@ -5,8 +5,8 @@
   include_context 'clean-up builder'
 
   before(:all) do
-    RgGen.enable(:global, [:bus_width, :address_width, :enable_wide_register, :library_name])
-    RgGen.enable(:register_block, [:name, :byte_size])
+    RgGen.enable(:global, [:address_width, :enable_wide_register, :library_name])
+    RgGen.enable(:register_block, [:name, :byte_size, :bus_width])
     RgGen.enable(:register_file, [:name, :offset_address, :size])
     RgGen.enable(:register, [:name, :offset_address, :size, :type])
     RgGen.enable(:register, :type, [:external, :indirect])

diff --git a/spec/rggen/vhdl/register_block/protocol/apb_spec.rb b/spec/rggen/vhdl/register_block/protocol/apb_spec.rb
@@ -5,8 +5,8 @@
   include_context 'clean-up builder'
 
   before(:all) do
-    RgGen.enable(:global, [:bus_width, :address_width, :enable_wide_register, :library_name])
-    RgGen.enable(:register_block, [:name, :protocol, :byte_size])
+    RgGen.enable(:global, [:address_width, :enable_wide_register, :library_name])
+    RgGen.enable(:register_block, [:name, :protocol, :byte_size, :bus_width])
     RgGen.enable(:register_block, :protocol, [:apb])
     RgGen.enable(:register, [:name, :offset_address, :size, :type])
     RgGen.enable(:register, :type, [:external])

diff --git a/spec/rggen/vhdl/register_block/protocol/axi4lite_spec.rb b/spec/rggen/vhdl/register_block/protocol/axi4lite_spec.rb
@@ -5,8 +5,8 @@
   include_context 'clean-up builder'
 
   before(:all) do
-    RgGen.enable(:global, [:bus_width, :address_width, :enable_wide_register, :library_name])
-    RgGen.enable(:register_block, [:name, :protocol, :byte_size])
+    RgGen.enable(:global, [:address_width, :enable_wide_register, :library_name])
+    RgGen.enable(:register_block, [:name, :protocol, :byte_size, :bus_width])
     RgGen.enable(:register_block, :protocol, [:axi4lite])
     RgGen.enable(:register, [:name, :offset_address, :size, :type])
     RgGen.enable(:register, :type, [:external])

diff --git a/spec/rggen/vhdl/register_block/protocol/native_spec.rb b/spec/rggen/vhdl/register_block/protocol/native_spec.rb
@@ -5,8 +5,8 @@
   include_context 'clean-up builder'
 
   before(:all) do
-    RgGen.enable(:global, [:bus_width, :address_width, :enable_wide_register, :library_name])
-    RgGen.enable(:register_block, [:name, :protocol, :byte_size])
+    RgGen.enable(:global, [:address_width, :enable_wide_register, :library_name])
+    RgGen.enable(:register_block, [:name, :protocol, :byte_size, :bus_width])
     RgGen.enable(:register_block, :protocol, [:native])
     RgGen.enable(:register, [:name, :offset_address, :size, :type])
     RgGen.enable(:register, :type, [:external])

diff --git a/spec/rggen/vhdl/register_block/protocol/wishbone_spec.rb b/spec/rggen/vhdl/register_block/protocol/wishbone_spec.rb
@@ -5,8 +5,8 @@
   include_context 'clean-up builder'
 
   before(:all) do
-    RgGen.enable(:global, [:bus_width, :address_width, :enable_wide_register, :library_name])
-    RgGen.enable(:register_block, [:name, :protocol, :byte_size])
+    RgGen.enable(:global, [:address_width, :enable_wide_register, :library_name])
+    RgGen.enable(:register_block, [:name, :protocol, :byte_size, :bus_width])
     RgGen.enable(:register_block, :protocol, [:wishbone])
     RgGen.enable(:register, [:name, :offset_address, :size, :type])
     RgGen.enable(:register, :type, [:external])

diff --git a/spec/rggen/vhdl/register_block/protocol_spec.rb b/spec/rggen/vhdl/register_block/protocol_spec.rb
@@ -12,8 +12,8 @@
       vhdl {}
     end
 
-    RgGen.enable(:global, [:bus_width, :address_width])
-    RgGen.enable(:register_block, [:protocol, :byte_size])
+    RgGen.enable(:global, [:address_width])
+    RgGen.enable(:register_block, [:protocol, :byte_size, :bus_width])
     RgGen.enable(:register_block, :protocol, :foo)
   end
 

diff --git a/spec/rggen/vhdl/register_file/vhdl_top_spec.rb b/spec/rggen/vhdl/register_file/vhdl_top_spec.rb
@@ -5,8 +5,8 @@
   include_context 'clean-up builder'
 
   before(:all) do
-    RgGen.enable(:global, [:bus_width, :address_width, :enable_wide_register, :library_name])
-    RgGen.enable(:register_block, [:name, :byte_size])
+    RgGen.enable(:global, [:address_width, :enable_wide_register, :library_name])
+    RgGen.enable(:register_block, [:name, :byte_size, :bus_width])
     RgGen.enable(:register_file, [:name, :offset_address, :size])
     RgGen.enable(:register, [:name, :offset_address, :size, :type])
     RgGen.enable(:register, :type, [:external, :indirect])

diff --git a/spec/support/shared_context.rb b/spec/support/shared_context.rb
@@ -89,8 +89,8 @@ def not_have_signal(*args, &body)
   include_context 'vhdl common'
 
   before(:all) do
-    RgGen.enable(:global, [:bus_width, :address_width, :enable_wide_register, :library_name])
-    RgGen.enable(:register_block, :byte_size)
+    RgGen.enable(:global, [:address_width, :enable_wide_register, :library_name])
+    RgGen.enable(:register_block, [:byte_size, :bus_width])
     RgGen.enable(:register_file, [:name, :size, :offset_address])
     RgGen.enable(:register, [:name, :size, :type, :offset_address])
     RgGen.enable(:bit_field, [:name, :bit_assignment, :initial_value, :reference, :type])