add avalon support (#43, rggen/rggen#97)

lib/rggen/vhdl.rb

@@ -27,6 +27,7 @@
     'vhdl/register_block/protocol',
     'vhdl/register_block/protocol/apb',
     'vhdl/register_block/protocol/axi4lite',
+    'vhdl/register_block/protocol/avalon',
     'vhdl/register_block/protocol/wishbone',
     'vhdl/register_block/protocol/native',
     'vhdl/register_file/vhdl_top',

lib/rggen/vhdl/register_block/protocol/avalon.erb

@@ -0,0 +1,35 @@
+u_adapter: entity <%= library_name %>.rggen_avalon_adapter
+  generic map (
+    ADDRESS_WIDTH       => <%= address_width %>,
+    LOCAL_ADDRESS_WIDTH => <%= local_address_width %>,
+    BUS_WIDTH           => <%= bus_width %>,
+    REGISTERS           => <%= total_registers %>,
+    PRE_DECODE          => <%= pre_decode %>,
+    BASE_ADDRESS        => <%= base_address %>,
+    BYTE_SIZE           => <%= byte_size %>,
+    ERROR_STATUS        => <%= error_status %>,
+    INSERT_SLICER       => <%= insert_slicer %>
+  )
+  port map (
+    i_clk                 => <%= register_block.clock %>,
+    i_rst_n               => <%= register_block.reset %>,
+    i_read                => <%= read %>,
+    i_write               => <%= write %>,
+    i_address             => <%= address %>,
+    i_byteenable          => <%= byteenable %>,
+    i_writedata           => <%= writedata %>,
+    o_waitrequest         => <%= waitrequest %>,
+    o_readdatavalid       => <%= readdatavalid %>,
+    o_writeresponsevalid  => <%= writeresponsevalid %>,
+    o_response            => <%= response %>,
+    o_readdata            => <%= readdata %>,
+    o_register_valid      => <%= register_block.register_valid %>,
+    o_register_access     => <%= register_block.register_access %>,
+    o_register_address    => <%= register_block.register_address %>,
+    o_register_write_data => <%= register_block.register_write_data %>,
+    o_register_strobe     => <%= register_block.register_strobe %>,
+    i_register_active     => <%= register_block.register_active %>,
+    i_register_ready      => <%= register_block.register_ready %>,
+    i_register_status     => <%= register_block.register_status %>,
+    i_register_read_data  => <%= register_block.register_read_data %>
+  );

lib/rggen/vhdl/register_block/protocol/avalon.rb

@@ -0,0 +1,40 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register_block, :protocol, :avalon) do
+  vhdl do
+    build do
+      input :read, {
+        name: 'i_read'
+      }
+      input :write, {
+        name: 'i_write'
+      }
+      input :address, {
+        name: 'i_address', width: address_width
+      }
+      input :byteenable, {
+        name: 'i_byteenable', width: bus_width / 8
+      }
+      input :writedata, {
+        name: 'i_writedata', width: bus_width
+      }
+      output :waitrequest, {
+        name: 'o_waitrequest'
+      }
+      output :readdatavalid, {
+        name: 'o_readdatavalid'
+      }
+      output :writeresponsevalid, {
+        name: 'o_writeresponsevalid'
+      }
+      output :response, {
+        name: 'o_response', width: 2
+      }
+      output :readdata, {
+        name: 'o_readdata', width: bus_width
+      }
+    end
+
+    main_code :register_block, from_template: true
+  end
+end

lib/rggen/vhdl/register_block/protocol/native.erb

@@ -8,6 +8,7 @@ u_adapter: entity <%= library_name %>.rggen_native_adapter
     PRE_DECODE          => <%= pre_decode %>,
     BASE_ADDRESS        => <%= base_address %>,
     BYTE_SIZE           => <%= byte_size %>,
+    USE_READ_STROBE     => <%= use_read_strobe %>,
     ERROR_STATUS        => <%= error_status %>,
     INSERT_SLICER       => <%= insert_slicer %>
   )

lib/rggen/vhdl/register_block/protocol/native.rb

@@ -6,6 +6,9 @@
       generic :strobe_width, {
         name: 'STROBE_WIDTH', type: :positive, default: bus_width / 8
       }
+      generic :use_read_strobe, {
+        name: 'USE_READ_STROBE', type: :boolean, default: false
+      }
 
       input :valid, { name: 'i_csrbus_valid' }
       input :access, { name: 'i_csrbus_access', width: 2 }

spec/rggen/vhdl/register_block/protocol/avalon_spec.rb

@@ -0,0 +1,130 @@
+# frozen_string_literal: true
+
+RSpec.describe 'register_block/protocol/avalon' do
+  include_context 'vhdl common'
+  include_context 'clean-up builder'
+
+  before(:all) do
+    RgGen.enable(:global, [:address_width, :enable_wide_register, :library_name])
+    RgGen.enable(:register_block, [:name, :protocol, :byte_size, :bus_width])
+    RgGen.enable(:register_block, :protocol, [:avalon])
+    RgGen.enable(:register, [:name, :offset_address, :size, :type])
+    RgGen.enable(:register, :type, [:external])
+    RgGen.enable(:register_block, [:vhdl_top])
+  end
+
+  let(:address_width) do
+    16
+  end
+
+  let(:bus_width) do
+    32
+  end
+
+  let(:library_name) do
+    ['work', 'foo_lib'].sample
+  end
+
+  let(:register_block) do
+    create_register_block do
+      name 'block_0'
+      byte_size 256
+      register { name 'register_0'; offset_address 0x00; size [1]; type :external }
+      register { name 'register_1'; offset_address 0x10; size [1]; type :external }
+      register { name 'register_2'; offset_address 0x20; size [1]; type :external }
+    end
+  end
+
+  def create_register_block(&body)
+    configuration = create_configuration(
+      address_width: address_width, bus_width: bus_width,
+      protocol: :avalon, library_name: library_name
+    )
+    create_vhdl(configuration, &body).register_blocks.first
+  end
+
+  it 'avalon用のポート群を持つ' do
+    expect(register_block).to have_port(
+      :read,
+      name: 'i_read', direction: :in
+    )
+    expect(register_block).to have_port(
+      :write,
+      name: 'i_write', direction: :in
+    )
+    expect(register_block).to have_port(
+      :address,
+      name: 'i_address', direction: :in, width: 'ADDRESS_WIDTH'
+    )
+    expect(register_block).to have_port(
+      :byteenable,
+      name: 'i_byteenable', direction: :in, width: bus_width / 8
+    )
+    expect(register_block).to have_port(
+      :writedata,
+      name: 'i_writedata', direction: :in, width: bus_width
+    )
+    expect(register_block).to have_port(
+      :waitrequest,
+      name: 'o_waitrequest', direction: :out
+    )
+    expect(register_block).to have_port(
+      :readdatavalid,
+      name: 'o_readdatavalid', direction: :out
+    )
+    expect(register_block).to have_port(
+      :writeresponsevalid,
+      name: 'o_writeresponsevalid', direction: :out
+    )
+    expect(register_block).to have_port(
+      :response,
+      name: 'o_response', direction: :out, width: 2
+    )
+    expect(register_block).to have_port(
+      :readdata,
+      name: 'o_readdata', direction: :out, width: bus_width
+    )
+  end
+
+  describe '#generate_code' do
+    it 'rggen_avalon_adapterをインスタンスするコードを生成する' do
+      expect(register_block).to generate_code(:register_block, :top_down, <<~CODE)
+        u_adapter: entity #{library_name}.rggen_avalon_adapter
+          generic map (
+            ADDRESS_WIDTH       => ADDRESS_WIDTH,
+            LOCAL_ADDRESS_WIDTH => 8,
+            BUS_WIDTH           => 32,
+            REGISTERS           => 3,
+            PRE_DECODE          => PRE_DECODE,
+            BASE_ADDRESS        => BASE_ADDRESS,
+            BYTE_SIZE           => 256,
+            ERROR_STATUS        => ERROR_STATUS,
+            INSERT_SLICER       => INSERT_SLICER
+          )
+          port map (
+            i_clk                 => i_clk,
+            i_rst_n               => i_rst_n,
+            i_read                => i_read,
+            i_write               => i_write,
+            i_address             => i_address,
+            i_byteenable          => i_byteenable,
+            i_writedata           => i_writedata,
+            o_waitrequest         => o_waitrequest,
+            o_readdatavalid       => o_readdatavalid,
+            o_writeresponsevalid  => o_writeresponsevalid,
+            o_response            => o_response,
+            o_readdata            => o_readdata,
+            o_register_valid      => register_valid,
+            o_register_access     => register_access,
+            o_register_address    => register_address,
+            o_register_write_data => register_write_data,
+            o_register_strobe     => register_strobe,
+            i_register_active     => register_active,
+            i_register_ready      => register_ready,
+            i_register_status     => register_status,
+            i_register_read_data  => register_read_data
+          );
+      CODE
+    end
+  end
+end

spec/rggen/vhdl/register_block/protocol/native_spec.rb

@@ -43,11 +43,15 @@ def create_register_block(&)
     create_vhdl(configuration, &).register_blocks.first
   end
 
-  it 'ジェネリックSTROBE_WIDTHを持つ' do
+  it 'ジェネリックSTROBE_WIDTH/USE_READ_STROBEを持つ' do
     expect(register_block).to have_generic(
       :strobe_width,
       name: 'STROBE_WIDTH', type: :positive, default: bus_width / 8
     )
+    expect(register_block).to have_generic(
+      :use_read_strobe,
+      name: 'USE_READ_STROBE', type: :boolean, default: false
+    )
   end
 
   it 'rggen_bus_if用の信号群を持つ' do
@@ -98,6 +102,7 @@ def create_register_block(&)
             PRE_DECODE          => PRE_DECODE,
             BASE_ADDRESS        => BASE_ADDRESS,
             BYTE_SIZE           => 256,
+            USE_READ_STROBE     => USE_READ_STROBE,
             ERROR_STATUS        => ERROR_STATUS,
             INSERT_SLICER       => INSERT_SLICER
           )