Skip to content
@riscv

RISC-V

The Open-Standard Instruction Set Architecture
README.md

Pinned Loading

  1. riscv-isa-manual riscv-isa-manual Public

    RISC-V Instruction Set Manual

    TeX 3.9k 677

  2. docs-dev-guide docs-dev-guide Public

    Documentation developer guide

    TeX 98 35

  3. docs-spec-template docs-spec-template Public template

    Makefile 24 22

  4. docs-resources docs-resources Public

    CSS 34 18

Repositories

Showing 10 of 59 repositories
  • riscv-aia Public
    riscv/riscv-aia’s past year of commit activity
    Makefile 86 CC-BY-4.0 19 29 1 Updated Mar 1, 2025
  • composable-custom-extensions Public

    This task group will propose ISA extension(s) and non-ISA hardware and software interop interfaces to enable routine reuse and composition of a subcategory of custom extensions called composable extensions.

    riscv/composable-custom-extensions’s past year of commit activity
    Makefile 3 CC-BY-4.0 1 1 1 Updated Mar 1, 2025
  • sail-riscv Public

    Sail RISC-V model

    riscv/sail-riscv’s past year of commit activity
    Coq 503 188 96 (1 issue needs help) 77 Updated Feb 28, 2025
  • riscv-smmtt Public

    This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant security use cases e.g. confidential-computing, trusted platform services, fault isolation and so on.

    riscv/riscv-smmtt’s past year of commit activity
    Makefile 44 CC-BY-4.0 19 3 0 Updated Feb 27, 2025
  • riscv-fast-interrupt Public

    Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)

    riscv/riscv-fast-interrupt’s past year of commit activity
    Makefile 259 CC-BY-4.0 51 50 3 Updated Feb 27, 2025
  • riscv-performance-events Public

    RISC-V Performance Events Specification

    riscv/riscv-performance-events’s past year of commit activity
    Makefile 4 CC-BY-4.0 3 0 1 Updated Feb 26, 2025
  • riscv-cheri Public

    This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.

    riscv/riscv-cheri’s past year of commit activity
    Python 62 CC-BY-4.0 35 41 (2 issues need help) 5 Updated Feb 26, 2025
  • riscv-debug-spec Public

    Working Draft of the RISC-V Debug Specification Standard

    riscv/riscv-debug-spec’s past year of commit activity
    Python 474 95 57 6 Updated Feb 26, 2025
  • riscv-sdtrigepm Public Forked from riscv/riscv-isa-manual

    Sdtrig Effective Privilege Mode (Sdtrigepm) Fast-track ISA Extension

    riscv/riscv-sdtrigepm’s past year of commit activity
    TeX 0 CC-BY-4.0 694 0 0 Updated Feb 24, 2025
  • riscv-isa-manual Public

    RISC-V Instruction Set Manual

    riscv/riscv-isa-manual’s past year of commit activity
    TeX 3,905 CC-BY-4.0 677 217 (2 issues need help) 14 Updated Feb 24, 2025
View all repositories

Most used topics

Loading…