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@riscv-non-isa

RISC-V Non-ISA Specifications

The Open-Standard Instruction Set Architecture
README.md

Welcome to the RISC-V Non-ISA Specifications 👋

RISC-V Logo

Non-ISA specifications do not add new instructions, create or change opcodes, or in any way modify the RISC-V ISA. They do help us to develop an ecosystem around the ISA Specifications.

Things you'll find here include:

  • ABI Documentation
  • Architecture Tests
  • Specifications like Debug, Processor Trace, and Software Interrupts

If you don't find what you're looking for here, try one of our other GitHub organizations:

Popular repositories Loading

  1. riscv-asm-manual riscv-asm-manual Public

    RISC-V Assembly Programmer's Manual

    Makefile 1.5k 240

  2. riscv-elf-psabi-doc riscv-elf-psabi-doc Public

    A RISC-V ELF psABI Document

    Python 720 165

  3. riscv-arch-test riscv-arch-test Public

    Assembly 523 206

  4. riscv-sbi-doc riscv-sbi-doc Public

    Documentation for the RISC-V Supervisor Binary Interface

    Makefile 356 94

  5. rvv-intrinsic-doc rvv-intrinsic-doc Public

    C 298 90

  6. riscv-trace-spec riscv-trace-spec Public

    RISC-V Processor Trace Specification

    C 168 48

Repositories

Showing 10 of 35 repositories
  • riscv-c-api-doc Public

    Documentation of the RISC-V C API

    riscv-non-isa/riscv-c-api-doc’s past year of commit activity
    Makefile 74 CC-BY-4.0 42 17 11 Updated Dec 11, 2024
  • riscv-toolchain-conventions Public

    Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains

    riscv-non-isa/riscv-toolchain-conventions’s past year of commit activity
    Makefile 146 CC-BY-4.0 36 15 7 Updated Dec 11, 2024
  • riscv-iommu Public

    RISC-V IOMMU Specification

    riscv-non-isa/riscv-iommu’s past year of commit activity
    C 99 CC-BY-4.0 18 2 2 Updated Dec 11, 2024
  • riscv-cbqri Public

    This repo holds the work area and revisions of a QoS register interface for caches and memory controllers specification. The QoS register interface is a non-ISA specification that supports configuring resource allocations to applications and monitoring the resource usage by applications.

    riscv-non-isa/riscv-cbqri’s past year of commit activity
    Makefile 4 CC-BY-4.0 8 0 0 Updated Dec 11, 2024
  • riscv-ras-eri Public

    The (RAS Error-record Register Interface) RERI provides a specification to augment RAS features in RISC-V SOC hardware to standardize reporting and logging of errors by means of a memory-mapped register interface to enable error detection, provide the facility to log the detected errors (including their severity, nature, and location), and confi…

    riscv-non-isa/riscv-ras-eri’s past year of commit activity
    TeX 9 CC-BY-4.0 5 0 0 Updated Dec 11, 2024
  • server-soc Public

    The repo holds the draft non-ISA Server SoC specification being developed by the Server SoC specification TG and to release intermediate releases of the specification on milestones. Further downstream this repo will be used to release specifications for public review.

    riscv-non-isa/server-soc’s past year of commit activity
    TeX 20 CC-BY-4.0 8 2 1 Updated Dec 11, 2024
  • server-soc-ts Public

    Test suite for Server SoC

    riscv-non-isa/server-soc-ts’s past year of commit activity
    3 Apache-2.0 5 0 0 Updated Dec 10, 2024
  • riscv-asm-manual Public

    RISC-V Assembly Programmer's Manual

    riscv-non-isa/riscv-asm-manual’s past year of commit activity
    Makefile 1,451 CC-BY-4.0 240 7 9 Updated Dec 9, 2024
  • tg-nexus-trace Public

    RISC-V Nexus Trace TG documentation and reference code

    riscv-non-isa/tg-nexus-trace’s past year of commit activity
    C 45 CC-BY-4.0 34 5 1 Updated Dec 9, 2024
  • riscv-brs Public

    The Boot and Runtime Services (BRS) specification provides the software requirements for system vendors and Operating System Vendors (OSVs) to interoperate with one another by providing expectations for the Operating System (OS) to utilize in acts of device discovery, system management, and other rich operations provided in this specification.

    riscv-non-isa/riscv-brs’s past year of commit activity
    TeX 43 CC-BY-4.0 14 15 2 Updated Dec 9, 2024
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