qos.bib

@electronic{PRIV,
  title = {RISC-V Instruction Set Manual, Volume II: Privileged Architecture},
  url = {https://github.com/riscv/riscv-isa-manual},
  year = {}
}
@electronic{IOMMU,
  title = {RISC-V IOMMU Architecture Specification},
  url = {https://github.com/riscv-non-isa/riscv-iommu}
}
@electronic{SSQOSID,
  title = {RISC-V Quality-of-Service (QoS) Identifiers},
  url = {https://github.com/riscv/riscv-ssqosid}
}
@electronic{STATEEN,
  title = {RISC-V State Enable Extension},
  url = {https://drive.google.com/file/d/1dhI6OzVbejQbfwyBTuwK9U4VUmW8ii4o/view}
}
@INPROCEEDINGS{SSAMPLE,
  author={Thornock, N.C. and Flanagan, J.K.},
  booktitle={2000 Winter Simulation Conference Proceedings (Cat. No.00CH37165)},
  title={Facilitating level three cache studies using set sampling},
  year={2000},
  volume={1},
  number={},
  pages={471-479 vol.1},
  doi={10.1109/WSC.2000.899754}
}  
@article{PTCAMP,
  author = {Du Bois, Kristof and Eyerman, Stijn and Eeckhout, Lieven},
  title = {Per-Thread Cycle Accounting in Multicore Processors},
  year = {2013},
  issue_date = {January 2013},
  publisher = {Association for Computing Machinery},
  address = {New York, NY, USA},
  volume = {9},
  number = {4},
  issn = {1544-3566},
  url = {https://doi.org/10.1145/2400682.2400688},
  doi = {10.1145/2400682.2400688},
  journal = {ACM Trans. Archit. Code Optim.},
  month = {jan},
  articleno = {29},
  numpages = {22},
}
@inproceedings{HERACLES,
  author = {Lo, David and Cheng, Liqun and Govindaraju, Rama and Ranganathan, Parthasarathy and Kozyrakis, Christos},
  title = {Heracles: Improving Resource Efficiency at Scale},
  year = {2015},
  isbn = {9781450334020},
  publisher = {Association for Computing Machinery},
  address = {New York, NY, USA},
  url = {https://doi.org/10.1145/2749469.2749475},
  doi = {10.1145/2749469.2749475},
  booktitle = {Proceedings of the 42nd Annual International Symposium on Computer Architecture},
  pages = {450–462},
  numpages = {13},
  location = {Portland, Oregon},
  series = {ISCA '15}
}