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Table 3 in riscv-elf.adoc (currently section 8.4, table 9 in the latest release document) lists the target encodings and computation for all types of relocation. The table gives the type of instruction or data modified and informally states the range of the relocation (e.g., 12-bit PC-relative branch offset for BRANCH).
Based on my experience implementing RISC-V relocations for the zephyr RTOS, I think the table would be easier to read and implement if it would instead state the range of the relocation as an explicit interval, e.g., [-4096, +4094] for the BRANCH relocation.
If you agree this is useful, I will submit a PR accordingly.
The text was updated successfully, but these errors were encountered:
Table 3 in riscv-elf.adoc (currently section 8.4, table 9 in the latest release document) lists the target encodings and computation for all types of relocation. The table gives the type of instruction or data modified and informally states the range of the relocation (e.g., 12-bit PC-relative branch offset for
BRANCH
).Based on my experience implementing RISC-V relocations for the zephyr RTOS, I think the table would be easier to read and implement if it would instead state the range of the relocation as an explicit interval, e.g., [-4096, +4094] for the
BRANCH
relocation.If you agree this is useful, I will submit a PR accordingly.
The text was updated successfully, but these errors were encountered: