Added More Vector Arithmetic Instruction Support #190
Merged
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Added support for even more vector arithmetic instructions:
Also redesigned how the vector uop generator handles vector instructions when only 1 uop is needed (e.g, LMUL = 1, certain vector instructions are not sequenced). The vector uop generator will always generate at least one uop which will be used in place of the "parent" instruction. This is necessary because some vector instructions require the source and/or dest registers be added. For example, the multiply-add vector instructions need to have their destination added as one of their sources.
There are two categories of vector arithmetic instructions that cannot be supported correctly because of issues with Mavis:
Once these Mavis issues are resolved, all vector arithmetic instructions will be supported by Olympia.