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Libfdt support & local Timer node addition. #112

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This PR adds support for libfdt and adds local timer node into the device tree. It is just a temporary patch only meant for linux capable boards. I hope future replacement of bbl will contain libfdt support inbuilt. Thus 1st patch will not be required afterwards.
That's why it is rebased on the commit id 5a0e3e5 which was referred in freedom-u-sdk.

Please let me know if I should rebase these patches on top of some other commit.

BBL performs in memory operations to modify FDT entries. This is
perfectly fine for existing use case where only some properties are
modified. However, this is not an feasible option in case of
multiple subnode addition.

Add libfdt support by linking the libfdt source directly.

I understand that libfdt might have increased the size of bbl
significantly. However, this is just a temporary patch only meant
for linux capable boards. Once we have a proper boot loader with
separate firmware layer, this patch will no longer be required.
For example, u-boot has already support for libfdt. Thus, this
patch will be redundant and can be removed.

Signed-off-by: Atish Patra <[email protected]>
The present device tree is loaded from ROM and doesn't have
an entry for local timer. Linux kernel needs a local timer
node so that timer interrupt can be registered as a regular
interrupt under HLIC irq domain.

Signed-off-by: Atish Patra <[email protected]>
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atishp04 commented Jul 1, 2018

FYI: I have reused code from glibc in util/bcopy.c & string.c. It was all under openBSD license. So I thought it would be okay to directly include. If not, please advise.

atishp04 added a commit to atishp04/riscv-linux that referenced this pull request Jul 9, 2018
Currently, ther timer interrupt handleri(riscv_timer_interrupt())
is invoked directly from the arch handler. This
approach creates interwinding of driver and architecture
code which is not ideal.

Register timer interrupt as a per cpu based irq behind
generic Linux IRQ infrastructure. As the local timer node
is directly connected to individual harts, HLIC acts as
the parent irq domain.

This patch requires necessary bbl changes that adds timer
node in device tree which can be found here.

riscv-software-src/riscv-pk#112

Before the patch
---------------------------------------------------
     CPU1 CPU2 CPU3 CPU4
 21: 12    8    6    5  riscv,plic0,c000000  53  eth0
 37: 0     0    0    0  riscv,plic0,c000000  32  xilinx-pcie
 43: 0     0    0    0  riscv,plic0,c000000   4  10010000.serial
 44: 0     0    0    0  riscv,plic0,c000000   5  10011000.serial
 45: 0     0    0    0  riscv,plic0,c000000  51  10040000.spi
 46: 0     0    0    0  riscv,plic0,c000000  52  10041000.spi
 47: 25    1    26   50  riscv,plic0,c000000   6  10050000.spi

After the patch
---------------------------------------------------
      CPU1 CPU2 CPU3 CPU4
  5:  271   0    0    0    riscv,cpu_intc,1   5  local_timer
  6:  0     307  0    0    riscv,cpu_intc,2   5  local_timer
  7:  0     0    303  0    riscv,cpu_intc,3   5  local_timer
  8:  0     0    0    223  riscv,cpu_intc,4   5  local_timer
 47:  337   489  389  35   riscv,plic0,c000000   4  10010000.serial
 48:  0     0    0    0    riscv,plic0,c000000   5  10011000.serial
 49:  0     0    0    0    riscv,plic0,c000000  51  10040000.spi
 50:  0     0    0    0    riscv,plic0,c000000  52  10041000.spi
 51:  2     14   47   39   riscv,plic0,c000000   6  10050000.spi

Signed-off-by: Atish Patra <[email protected]>
atishp04 added a commit to atishp04/riscv-linux that referenced this pull request Jul 9, 2018
Currently, the timer interrupt handler(riscv_timer_interrupt())
is invoked directly from the arch handler. This
approach creates interwinding of driver and architecture
code which is not ideal.

Even if the all timer hwirq have same irq number, they are discrete
interrupts connected to each core. Moreover, HLIC is modelled in a
way that there are individual HLIC per hart. Thus, register timer
interrupt as an individual irq under generic Linux IRQ management
framework instead of per-cpu irq. Individual HLIC acts as the parent
irq domain.

This patch requires necessary bbl changes that adds timer
node in device tree which can be found here.

riscv-software-src/riscv-pk#112

Before the patch
---------------------------------------------------
     CPU1 CPU2 CPU3 CPU4
 21: 12    8    6    5  riscv,plic0,c000000  53  eth0
 37: 0     0    0    0  riscv,plic0,c000000  32  xilinx-pcie
 43: 0     0    0    0  riscv,plic0,c000000   4  10010000.serial
 44: 0     0    0    0  riscv,plic0,c000000   5  10011000.serial
 45: 0     0    0    0  riscv,plic0,c000000  51  10040000.spi
 46: 0     0    0    0  riscv,plic0,c000000  52  10041000.spi
 47: 25    1    26   50  riscv,plic0,c000000   6  10050000.spi

After the patch
---------------------------------------------------
      CPU1 CPU2 CPU3 CPU4
  5:  271   0    0    0    riscv,cpu_intc,1   5  local_timer
  6:  0     307  0    0    riscv,cpu_intc,2   5  local_timer
  7:  0     0    303  0    riscv,cpu_intc,3   5  local_timer
  8:  0     0    0    223  riscv,cpu_intc,4   5  local_timer
 47:  337   489  389  35   riscv,plic0,c000000   4  10010000.serial
 48:  0     0    0    0    riscv,plic0,c000000   5  10011000.serial
 49:  0     0    0    0    riscv,plic0,c000000  51  10040000.spi
 50:  0     0    0    0    riscv,plic0,c000000  52  10041000.spi
 51:  2     14   47   39   riscv,plic0,c000000   6  10050000.spi

Signed-off-by: Atish Patra <[email protected]>
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