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In section 3.1.2 of the CLIC spec we have this note:
"The highest numbered interrupt wins in a tie (when privilege mode, level and priority are all identical). This is the same as in CLINT interrupt mode, but different than the PLIC."
I've not been able to find where the CLINT interrupt mode is defined to have highest numbered interrupt winning in a tie.
The Privileged ISA manual (20240411) has a note in section 3.1.9 which states:
"The platform-specific machine-level interrupt sources in bits 16 and above have platformspecific priority, but are typically chosen to have the highest service priority to support very fast local vectored interrupts."
The statement in the CLIC spec appears to be in conflict with this.
The text was updated successfully, but these errors were encountered:
I think the note is unnecessary. There is a ton of interrupt controllers specs in RISC-V. Makes no sense that every interrupt controller spec states how it does prioritization differently. This is bound to be incomplete and redundant.
In section 3.1.2 of the CLIC spec we have this note:
"The highest numbered interrupt wins in a tie (when privilege mode, level and priority are all identical). This is the same as in CLINT interrupt mode, but different than the PLIC."
I've not been able to find where the CLINT interrupt mode is defined to have highest numbered interrupt winning in a tie.
The Privileged ISA manual (20240411) has a note in section 3.1.9 which states:
"The platform-specific machine-level interrupt sources in bits 16 and above have platformspecific priority, but are typically chosen to have the highest service priority to support very fast local vectored interrupts."
The statement in the CLIC spec appears to be in conflict with this.
The text was updated successfully, but these errors were encountered: