add vivado skip

ru551n · Jun 16, 2024 · a95bbb5 · a95bbb5
1 parent 97773e9
commit a95bbb5
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Showing 2 changed files with 8 additions and 4 deletions.
diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml
@@ -19,4 +19,4 @@ jobs:
       - name: Gitman update
         run: gitman update
       - name: Run simulations
-        run: python run.py
+        run: python run.py --vivado-skip
diff --git a/run.py b/run.py
@@ -10,8 +10,10 @@
 REPO_ROOT = Path(__file__).parent.resolve()
 TSFPGA_PATH = REPO_ROOT / "tsfpga"
 VUNIT_PATH = REPO_ROOT / "vunit"
+HDL_REGISTERS_PATH = REPO_ROOT / "vunit"
 sys.path.insert(0, str(TSFPGA_PATH))
 sys.path.insert(0, str(VUNIT_PATH))
+sys.path.insert(0, str(HDL_REGISTERS_PATH))
 
 from tsfpga.examples.simulation_utils import create_vhdl_ls_configuration
 
@@ -34,11 +36,13 @@ def main():
     args = cli.parse_args()
 
     modules = get_modules(modules_folder=REPO_ROOT / "modules")
-    modules_no_sim = get_modules(modules_folder=REPO_ROOT / "hdl-module" / "modules")
+    modules += get_modules(modules_folder=REPO_ROOT / "hdl-module" / "modules")
 
     simulation_project = SimulationProject(args=args)
-    simulation_project.add_modules(args=args, modules=modules, modules_no_sim=modules_no_sim)
-    simulation_project.add_vivado_simlib()
+    simulation_project.add_modules(args=args, modules=modules)
+
+    if not args.vivado_skip:
+        simulation_project.add_vivado_simlib()
 
     create_vhdl_ls_configuration(
         output_path=REPO_ROOT,