Fix STM32-patched CI

CHANGELOG.md

@@ -7,6 +7,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/).
 
 ## [Unreleased]
 
+- Fix STM32-patched CI
 - Fix `enumeratedValues` with `isDefault` only
 
 ## [v0.33.4] - 2024-06-16

ci/script.sh

@@ -503,7 +503,7 @@ main() {
             echo '[dependencies.riscv-rt]' >> $td/Cargo.toml
             echo 'version = "0.8.0"' >> $td/Cargo.toml
 
-            test_svd_for_target riscv https://raw.githubusercontent.com/riscv-rust/e310x/master/e310x.svd
+            test_svd_for_target riscv https://raw.githubusercontent.com/riscv-rust/e310x/master/e310x/e310x.svd
             test_svd_for_target riscv https://raw.githubusercontent.com/riscv-rust/k210-pac/master/k210.svd
             test_svd_for_target riscv https://raw.githubusercontent.com/riscv-rust/fu540-pac/master/fu540.svd
         ;;
@@ -572,6 +572,15 @@ main() {
         ;;
 
         STM32-patched)
+            echo '[dependencies.critical-section]' >> $td/Cargo.toml
+            echo 'version = "1.0"' >> $td/Cargo.toml
+            echo 'optional = true' >> $td/Cargo.toml
+
+            echo '[features]' >> $td/Cargo.toml
+            echo 'default = ["critical-section", "rt"]' >> $td/Cargo.toml
+            echo 'rt = ["cortex-m-rt/device"]' >> $td/Cargo.toml
+            echo 'atomics = []' >> $td/Cargo.toml
+
             # OK
             test_patched_stm32 stm32f0x2
             test_patched_stm32 stm32f103

ci/svd2rust-regress/tests.yml

@@ -2102,7 +2102,7 @@
 - arch: riscv
   mfgr: SiFive
   chip: E310x
-  svd_url: https://raw.githubusercontent.com/riscv-rust/e310x/master/e310x.svd
+  svd_url: https://raw.githubusercontent.com/riscv-rust/e310x/master/e310x/e310x.svd
   should_pass: false
   run_when: never
 - arch: msp430