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serial: implement receive FIFO flush via FCR #103

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serial: implement receive FIFO flush via FCR #103

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Commits on Nov 22, 2024

  1. serial: implement receive FIFO flush via FCR 

    The FIFO Control Register (FCR) controls the behavior of the receive
and transmit FIFO buffers of the device. The current implementation
does not emulate this register, as FIFO buffers are always enabled.
However, there are two bits in this register that control flushing of
said FIFOS. The transmission FIFO is already flushed by the current
implementation on every write, but the receive FIFO is not. This is
problematic, as some driver implementations (e.g. FreeBSD's) rely on
being able to clear this buffer via the corresponding bit.

Implement the correct behavior when a driver sets this bit by clearing
`in_buffer`. Since there is no more data in the receive FIFO, the
data-ready bit in the Line Status Register (LSR) must be cleared as
well, in case it was set.

Fixes: rust-vmm#83
Signed-off-by: Carlos López <[email protected]>
    @00xc
    00xc committed Nov 22, 2024
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  2. serial: add a test for receive FIFO flushing 

    Add a test that checks that flushing the receive FIFO results in the
correct behavior, i.e. `in_buffer` is cleared.

Signed-off-by: Carlos López <[email protected]>
    @00xc
    00xc committed Nov 22, 2024
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