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add CASE version
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jasonbelt committed Aug 22, 2024
1 parent cdd94ca commit 48560dc
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/.aadlbin-gen/
18 changes: 18 additions & 0 deletions basic/test_data_port_periodic_three_domains_CASE/aadl/.project
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<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>test_data_port_periodic_three_domains_CASE</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.xtext.ui.shared.xtextBuilder</name>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>org.osate.core.aadlnature</nature>
<nature>org.eclipse.xtext.ui.shared.xtextNature</nature>
</natures>
</projectDescription>
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#include <camkes.h>
#include <stdio.h>
#include <sb_types.h>
#include <sb_producer_thread_i.h>

static int8_t _value;

void init(const int64_t *in_arg) {
printf("[%s] called\n", get_instance_name());
_value = 0;
}

void compute(const int64_t *in_arg) {
printf("---------------------------------------\n");
if (sb_write_port_write( &_value )) {
printf("[%s] Sent %d\n", get_instance_name(), _value);
_value = (_value + 1) % 500;
} else {
printf("[%s] Unable to send\n", get_instance_name());
}
}
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#include <camkes.h>
#include <stdio.h>
#include <sb_types.h>
#include <sb_consumer_thread_i.h>

void init(const int64_t *in_arg) {
printf("[%s] init called\n", get_instance_name());
}

void compute(const int64_t * in_arg) {
int8_t _value;

if (sb_read_port_read(&value)) {
printf("[%s] value {%d}\n", get_instance_name(), value);

if (sb_write_port_write( &_value )) {
printf("[%s] Sent %d\n", get_instance_name(), _value);
} else {
printf("[%s] Unable to send\n", get_instance_name());
}
} else {
printf("[%s] no value consumed.\n", get_instance_name());
}
}
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// Copyright 2020 Adventium Labs

// This is a kernel data structure.

#include <config.h>
#include <object/structures.h>
#include <model/statedata.h>

// An arbitrary hand generated schedule. The length is in seL4 ticks
// (2 ms default). This schedule should be generated from the AADL model
// using execution time and data flow latency specifications.
//
// Pacer runs at highest rate
//
// This schedule is single-rate, 1Hz, run each thread at 200ms ticks for simplicity.
// Fill space in with domain 0.
//
// 4 T3 | - - - -
// 3 T2 | - - - -
// 2 T1 | - - - -
// 1 pacer | - - - -
// 0 dom0 |-- -- -- - ------ -- -- - ------ -- -- - ------ -- -- - ----
// |______________|______________________________________________\time
// seconds 1 2 3 4 /
//
// Major frame is 1 seconds, since destination has 1 second period
//
const dschedule_t ksDomSchedule[] = { // (1 tick == 2ms)
{ .domain = 0, .length = 100 }, // all other seL4 threads, init, 200ms
{ .domain = 1, .length = 5 }, // T1 10ms
{ .domain = 0, .length = 95 }, // domain0 190ms
{ .domain = 2, .length = 5 }, // T2 10ms
{ .domain = 0, .length = 95 }, // domain0 190ms
{ .domain = 3, .length = 5 }, // T3 10ms
{ .domain = 0, .length = 195 }, // domain0 390ms
// +
// -----------------------------------
// 1000ms
};

const word_t ksDomScheduleLength = sizeof(ksDomSchedule) / sizeof(dschedule_t);
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package test_data_port_periodic_three_domains
public
with Base_Types;
with HAMR;
with CASE_Scheduling;

----------------------------------------------------------------------
-- O n e
-- Thread T1
-- Process P1
--
-- thread specifies unit of temporal execution; depending on scheduling
-- model this can provide temporal isolation.
----------------------------------------------------------------------
thread T1
features
write_port: out data port Base_Types::Integer_8;
properties
Dispatch_Protocol => Periodic;
Period => 1000ms;
Compute_Execution_Time => 10ms .. 10ms;
Source_Text => ("behavior_code/T1.c");
Initialize_Entrypoint_Source_Text => "init";
Compute_Entrypoint_Source_Text => "compute";
end T1;

thread implementation T1.i
end T1.i;

-- process specifies boundary of spatial isolation
process P1
features
write_port: out data port Base_Types::Integer_8;
properties
CASE_Scheduling::Domain => 2;
end P1;

process implementation P1.i
subcomponents
t1: thread T1.i;
connections
write1: port t1.write_port -> write_port;
end P1.i;

----------------------------------------------------------------------
-- T w o
-- Thread T2
-- Process P2
--
----------------------------------------------------------------------
thread T2
features
read_port: in data port Base_Types::Integer_8;
write_port: out data port Base_Types::Integer_8;
properties
Dispatch_Protocol => Periodic;
Period => 1000ms;
Compute_Execution_Time => 10ms .. 10ms;
Source_Text => ("behavior_code/T2.c");
Initialize_Entrypoint_Source_Text => "init";
Compute_Entrypoint_Source_Text => "compute";
end T2;

thread implementation T2.i
end T2.i;

-- process specifies boundary of spatial isolation
process P2
features
read_port: in data port Base_Types::Integer_8;
write_port: out data port Base_Types::Integer_8;
properties
CASE_Scheduling::Domain => 3;
end P2;

process implementation P2.i
subcomponents
t2: thread T2.i;
connections
read2: port read_port -> t2.read_port;

write2: port t2.write_port -> write_port;
end P2.i;

----------------------------------------------------------------------
-- T h r e e
-- Thread T3
-- Process P3
--
----------------------------------------------------------------------
thread T3
features
read_port: in data port Base_Types::Integer_8;
properties
Dispatch_Protocol => Periodic;
Period => 1000ms;
Compute_Execution_Time => 10ms .. 10ms;
end T3;

thread implementation T3.i
end T3.i;

-- process specifies boundary of spatial isolation
process P3
features
read_port: in data port Base_Types::Integer_8;
properties
CASE_Scheduling::Domain => 4;
end P3;

process implementation P3.i
subcomponents
t3: thread T3.i;
connections
read3: port read_port -> t3.read_port;
end P3.i;


----------------------------------------------------------------------
processor proc
end proc;

processor implementation proc.impl
properties
Frame_Period => 1000ms;
Clock_Period => 2ms;
CASE_Scheduling::Max_Domain => 5;
CASE_Scheduling::Schedule_Source_Text => "domain_schedule.c";

end proc.impl;

virtual processor virt_proc
properties
Dispatch_Protocol => Periodic;
end virt_proc;

----------------------------------------------------------------------
system top
end top;

system implementation top.impl
subcomponents
proc: processor proc.impl;
virt_proc: virtual processor virt_proc;
p1: process P1.i;
p2: process P2.i;
p3: process P3.i;
connections
c1: port p1.write_port -> p2.read_port;
c2: port p2.write_port -> p3.read_port;
properties
Actual_Processor_Binding => (reference (virt_proc)) applies to P3;
Actual_Processor_Binding => (reference (proc)) applies to P1, P2, virt_proc;

HAMR::Platform => (seL4);

annex resolute {**
check HAMR_Guidelines
**};
end top.impl;

end test_data_port_periodic_three_domains;

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