add write for audio registers

src/cpu.cpp

@@ -61,17 +61,17 @@ CPU::CPU()
 	// TODO: check the initial state of IME
 	IMEFlag = -1;
 
-	IMEReg = false;
-}
+		IMEReg = false;
+	}
 
-// NOP just adds 4 cycles
-// Does nothing
-int CPU::NOP()
-{
-	reg_PC.dat += 1;
-	debugPrint("NOP\n");
-	return 4;
-}
+	// NOP just adds 4 cycles
+	// Does nothing
+	int CPU::NOP()
+	{
+		reg_PC.dat += 1;
+		debugPrint("NOP\n");
+		return 4;
+	}
 
 // LD BC, u16
 // Loads a 16 bit immediate value into BC

src/gameBoy.cpp

@@ -44,7 +44,7 @@ GBE::GBE()
 		printf("boot rom file not opened");
 
 	// Open the Game ROM
-	if ((gameROM = fopen("../tests/drmario.gb", "rb")) == NULL)
+	if ((gameROM = fopen("../tests/dmg_sound/rom_singles/01-registers.gb", "rb")) == NULL)
 		printf("game rom file not opened");
 
 	// Set the Boot ROM
@@ -129,7 +129,7 @@ void GBE::update()
 		// this runs at a freq of around 27 * freq(DIV) = 442368 Hz
 		// this is probably enough to implement APU
 		gbe_sound->stepAPU(s_Cycles);
-		// gbe_sound->test(s_Cycles);
+		gbe_sound->test(s_Cycles);
 		s_Cycles = 0;
 		s_Cycles += gbe_cpu->performInterrupt();
 		// printf("s_Cycles after: %d\n\n", s_Cycles);

src/mmap.cpp

@@ -44,6 +44,9 @@ MemoryMap::MemoryMap()
 	highRam = new Byte[0x007F];
 	memset(highRam, 0x00, 0x007F);
 
+	waveRam = new Byte[0x0010];
+	memset(waveRam, 0x00, 0x0010 );
+
 	// 1 byte Interrupt Enable Register
 	interruptEnableRegister = new Byte;
 
@@ -98,6 +101,8 @@ MemoryMap::MemoryMap()
 	// WX at 0xFF4B
 	reg_WX = ioPorts + 0x4B;
 
+	audioReg = ioPorts + 0x10;
+
 	joyPadState = new Byte;
 	*joyPadState = 0xFF;
 
@@ -222,8 +227,40 @@ bool MemoryMap::writeMemory(Word address, Byte value)
 		{
 			readInput(value);
 		}
-		//if (value != 0xFF)
-		//printf("0x%02x\n", ioPorts[0]);}
+
+		// Write to Audio Registers
+		else if (address >= 0xFF10 && address <=0xFF26){
+			// NR52
+			// only 7th bit is read/write
+			// others are read only
+			if (address == 0xFF26 ){
+				printf("value: %x\n NR52 before: %x\n", value, *(audioReg+NR52));
+				value = value >> 7;
+				*(audioReg + NR52) = (*(audioReg + NR52) & 0b0111111) | (value << 7);
+				printf("NR52 after: %x\n", *(ioPorts+0x10+NR52));
+				printf("NR52 after: %x\n\n", *(audioReg+NR52));
+				enableAPU = value;
+
+			}
+
+			if(enableAPU){
+				// ioPorts
+				// NR20 && NR40
+				// if( address == 0xFF15 || address == 0xFF1F)
+			}else {
+				for( int i= NR10; i <= NR52 ; i++ ){
+					*(audioReg+i) = 0x00;
+				}
+			}
+		}
+
+		// Write to Wave 
+		else if (address >= 0xFF30 && address <= 0xFF3F){
+			if(enableAPU){
+
+			}
+		}
+
 		else
 			ioPorts[address - 0xFF00] = value;
 	}

src/mmap.h

@@ -191,6 +191,19 @@ class MemoryMap
 	// Tells the number of bits of RAM Bank Number that are useful for RAM
 	Byte ramBankNumberMaskForRam;
 
+
+	// APU enable
+	bool enableAPU;
+
+	// Audio Registers
+	// NR10 - NR52
+	// FF10 - FF26 
+	Byte* audioReg;
+
+	// FF30–FF3F — Wave pattern RAM
+	// 16 Bytes
+	Byte* waveRam;
+
 public:
 	Byte* joyPadState;
 
@@ -328,4 +341,8 @@ class MemoryMap
 
 	// Change RAM Banking according to the set registers
 	void bankRam();
+
+	Byte getAudioReg(int regId);
+
+	Byte* getWaveRam() { return waveRam; }
 };

src/sound.cpp

@@ -133,9 +133,16 @@ void APU::test(int cycles)
 {
 	a+=cycles;
 	if(std::chrono::duration_cast<std::chrono::seconds>(std::chrono::high_resolution_clock::now() - start).count() >1){
-		printf("%d\n",a);
+		// printf("%d\n",a);
 		a=0;
 		start = std::chrono::high_resolution_clock::now();
+		Byte* ptr = mMap->getIoPorts();
+		// for (Byte i = 0; i < 128; i++)
+		// {
+
+		// 	printf("\t%x: %p\n", *ptr, ptr);
+		// 	ptr++;
+		// }
 	}
 
 }

src/types.h

@@ -7,4 +7,43 @@ typedef unsigned char Byte;
 typedef char SByte;
 typedef unsigned short Word;
 typedef signed short SWord;
-typedef unsigned int color;
+typedef unsigned int color;
+enum AudioRegisters {
+    // NR1x
+    // FF10 - FF14
+    NR10,
+    NR11,
+    NR12,
+    NR13,
+    NR14,
+
+    // NR2x
+    // FF16 - FF19
+    NR20, // INVALID FF15
+    NR21,
+    NR22,
+    NR23,
+    NR24,
+
+    // NR3x
+    // FF1A - FF1E
+    NR30,
+    NR31,
+    NR32,
+    NR33,
+    NR34,
+
+    // NR4x
+    // FF20 - FF23
+    NR40, // INVALID FF1F
+    NR41,
+    NR42,
+    NR43,
+    NR44,
+
+    // NR5x
+    // FF24 - FF26
+    NR50,
+    NR51,
+    NR52
+};