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  1. SigasiProjectCreator SigasiProjectCreator Public

    Python scripts that help generating custom Sigasi Project and Libary configuration files

    Python 16 11

  2. sigasi_demos sigasi_demos Public

    SystemVerilog 9 3

  3. sigasi_insights sigasi_insights Public archive

    HTML 2 9

  4. sigasi_online_demo sigasi_online_demo Public

    Demo project

    VHDL 2

  5. sigasi_training sigasi_training Public

    Training material for Sigasi software

    VHDL 1

  6. sigasi_documentation_examples sigasi_documentation_examples Public

    This repository contains examples of documentation that has been generated using Sigasi Studio.

    HTML 1

Repositories

Showing 10 of 24 repositories
  • sigasi_theme Public archive

    Hugo theme used for Sigasi websites

    sigasi/sigasi_theme’s past year of commit activity
    JavaScript 0 BSD-3-Clause 0 0 0 Updated Apr 16, 2024
  • sigasi_insights Public archive
    sigasi/sigasi_insights’s past year of commit activity
    HTML 2 9 0 0 Updated Apr 9, 2024
  • SigasiProjectCreator Public

    Python scripts that help generating custom Sigasi Project and Libary configuration files

    sigasi/SigasiProjectCreator’s past year of commit activity
    Python 16 BSD-3-Clause 11 4 0 Updated Feb 27, 2024
  • Sigasi_CLI_in_CI_demo Public

    A demonstration of how the Sigasi CLI can be used in a CI/CD pipeline

    sigasi/Sigasi_CLI_in_CI_demo’s past year of commit activity
    SystemVerilog 0 BSD-3-Clause 0 1 0 Updated Feb 14, 2024
  • veresta-doc Public

    Generate Sigasi project documentation in CI

    sigasi/veresta-doc’s past year of commit activity
    SystemVerilog 0 0 0 0 Updated Dec 19, 2023
  • sigasi_online_demo Public

    Demo project

    sigasi/sigasi_online_demo’s past year of commit activity
    VHDL 2 BSD-3-Clause 0 0 0 Updated Aug 9, 2023
  • sigasi_demos Public
    sigasi/sigasi_demos’s past year of commit activity
    SystemVerilog 9 3 0 2 Updated May 26, 2023
  • uvm-in-vunit-tutorial-simple-adder Public Forked from naragece/uvm-testbench-tutorial-simple-adder

    A demonstration of how to run UVM tests in VUnit

    sigasi/uvm-in-vunit-tutorial-simple-adder’s past year of commit activity
    SystemVerilog 0 87 0 0 Updated Jun 27, 2022
  • sigasi_training Public

    Training material for Sigasi software

    sigasi/sigasi_training’s past year of commit activity
    VHDL 1 BSD-3-Clause 0 0 0 Updated Jan 5, 2022
  • sigasi-tmlanguage Public

    provide VHDL and SV syntax highlighting

    sigasi/sigasi-tmlanguage’s past year of commit activity
    0 BSD-3-Clause 0 0 0 Updated Dec 7, 2021
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