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publication.html

@@ -61,9 +61,8 @@ <h4>Accepted</h4>
 </ul>
 <h4>2025</h4>
 <ul>
-<li><p>[C36] Haomin Li, Fangxin Liu, Zongwu Wang, Dongxu Lyu, Shiyuan Huang, Ning Yang, <b>Qi Sun</b>, Zhuoran Song, Li Jiang, &lsquo;&lsquo;TAIL: Exploiting Temporal Asynchronous Execution for Efficient Spiking Neural Networks with Inter-Layer Parallelism&rsquo;&rsquo;, Design, Automation and Test in Europe Conference (<b>DATE</b>), Lyon, France, Mar. 31 - Apr. 02, 2025. </p>
-</li>
-<li><p>[C35] Fangxin Liu, Ning Yang, Zongwu Wang, Xuanpeng Zhu, Haidong Yao, Xiankui Xiong, <b>Qi Sun</b>, Li Jiang, &lsquo;&lsquo;OPS: Outlier-aware Precision-Slice Framework for LLM Acceleration&rsquo;&rsquo;, Design, Automation and Test in Europe Conference (<b>DATE</b>), Lyon, France, Mar. 31 - Apr. 02, 2025. </p>
+<li><p>[C36] Haomin Li, Fangxin Liu, Zongwu Wang, Dongxu Lyu, Shiyuan Huang, Ning Yang, <b>Qi Sun</b>, Zhuoran Song, Li Jiang, &lsquo;&lsquo;TAIL: Exploiting Temporal Asynchronous Execution for Efficient Spiking Neural Networks with Inter-Layer Parallelism&rsquo;&rsquo;, Design, Automation and Test in Europe Conference (<b>DATE</b>), Lyon, France, Mar. 31 - Apr. 02, 2025. 
+</p>
 </li>
 <li><p>[C34] Haonan Du, Chenyi Wen, Zhengrui Chen, Li Zhang, <b>Qi Sun</b>, Zheyu Yan, Cheng Zhuo, &lsquo;&lsquo;Algorithm-Hardware Co-design of a Unified Accelerator for Non-linear Functions in Transformers&rsquo;&rsquo;, Design, Automation and Test in Europe Conference (<b>DATE</b>), Lyon, France, Mar. 31 - Apr. 02, 2025. </p>
 </li>
@@ -172,7 +171,7 @@ <h4>2019</h4>
 <ul>
 <li><p>[C2] <b>Qi Sun</b>, Tinghuan Chen, Jin Miao, Bei Yu,&lsquo;&lsquo;Power-Driven DNN Dataflow Optimization on FPGA&rsquo;&rsquo;, IEEE/ACM International Conference on Computer-Aided Design (<b>ICCAD</b>), Westminster, CO, Nov. 4–7, 2019.</p>
 </li>
-<li><p>[C1] Wei Li, Yuzhe Ma, <b>Qi Sun</b>, Yibo Lin, Iris Hui-Ru Jiang, Bei Yu, David Z. Pan,&lsquo;&lsquo;OpenMPL: An Open Source Layout Decomposer&rsquo;&rsquo;, IEEE International Conference on ASIC (<b>ASICON</b>), Chongqing, China, Oct. 29–Nov. 1, 2019</p>
+<li><p>[C1] Wei Li, Yuzhe Ma, <b>Qi Sun</b>, Yibo Lin, Iris Hui-Ru Jiang, Bei Yu, David Z. Pan,&lsquo;&lsquo;OpenMPL: An Open Source Layout Decomposer&rsquo;&rsquo;, IEEE International Conference on ASIC (<b>ASICON</b>), Chongqing, China, Oct. 29–Nov. 1, 2019.</p>
 </li>
 </ul>
 </div> <!-- <div id="layout-content"> -->