commit 3d24568 upstream.

Add StarFive Kconfig option to select SoC specific and common drivers
required for these SoCs. Select subsystems required to boot so the
required drivers gets enabled by default.

Reviewed-by: Geert Uytterhoeven <[email protected]>
Acked-by: Palmer Dabbelt <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>

commit 3234d3a upstream.

Add compatible string for the StarFive JH7100 clint.

Reviewed-by: Geert Uytterhoeven <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>

commit 9ac1616 upstream.

Add compatible string for StarFive JH7100 plic.

Reviewed-by: Geert Uytterhoeven <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>

commit 38bb8a7 upstream.

Add all clock outputs for the StarFive JH7100 clock generator.

Based on work by Ahmad Fatoum for Barebox, with "JH7100_" prefixes added
to all definitions.

Acked-by: Rob Herring <[email protected]>
Acked-by: Stephen Boyd <[email protected]>
Signed-off-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>

commit af35098 upstream.

Add bindings for the clock generator on the JH7100 RISC-V SoC by
StarFive Ltd. This is a test chip for their upcoming JH7110 SoC.

Reviewed-by: Rob Herring <[email protected]>
Acked-by: Stephen Boyd <[email protected]>
Signed-off-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>

commit 4210be6 upstream.

Add a driver for the StarFive JH7100 clock generator.

Reviewed-by: Andy Shevchenko <[email protected]>
Acked-by: Stephen Boyd <[email protected]>
Signed-off-by: Geert Uytterhoeven <[email protected]>
Co-developed-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>

commit 810e287 upstream.

Add all resets for the StarFive JH7100 reset controller.

Based on work by Ahmad Fatoum for Barebox, with "JH7100_" prefixes added
to all definitions.

Acked-by: Rob Herring <[email protected]>
Signed-off-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>

commit d7d456a upstream.

Add bindings for the reset controller on the JH7100 RISC-V SoC by
StarFive Ltd. This is a test chip for their upcoming JH7110 SoC.

Reviewed-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>

commit 0be3a15 upstream.

Add a driver for the StarFive JH7100 reset controller.

Reviewed-by: Andy Shevchenko <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>

commit 3021114 upstream.

Add definitons for pins and GPIO input, output and output enable
signals on the StarFive JH7100 SoC.

Acked-by: Rob Herring <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>

commit 7431b39 upstream.

Add bindings for the GPIO/pin controller on the JH7100 RISC-V SoC by
StarFive Ltd. This is a test chip for their upcoming JH7110 SoC.

Reviewed-by: Linus Walleij <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>

commit ec648f6 upstream.

Add a combined pinctrl and GPIO driver for the JH7100 RISC-V SoC by
StarFive Ltd. This is a test chip for their upcoming JH7110 SoC, which
is said to feature only minor changes to these pinctrl/GPIO parts.

For each "GPIO" there are two registers for configuring the output and
output enable signals which may come from other peripherals. Among these
are two special signals that are constant 0 and constant 1 respectively.
Controlling the GPIOs from software is done by choosing one of these
signals. In other words the same registers are used for both pin muxing
and controlling the GPIOs, which makes it easier to combine the pinctrl
and GPIO driver in one.

I wrote the pinconf and pinmux parts, but the GPIO part of the code is
based on the GPIO driver in the vendor tree written by Huan Feng with
cleanups and fixes by Drew and me.

Datasheet: https://github.com/starfive-tech/JH7100_Docs/blob/main/JH7100%20Data%20Sheet%20V01.01.04-EN%20(4-21-2021).pdf
Reviewed-by: Andy Shevchenko <[email protected]>
Reviewed-by: Linus Walleij <[email protected]>
Co-developed-by: Huan Feng <[email protected]>
Signed-off-by: Huan Feng <[email protected]>
Co-developed-by: Drew Fustini <[email protected]>
Signed-off-by: Drew Fustini <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>

commit d0b65b1 upstream.

Add compatibles for the StarFive JH7100 uarts.

Reviewed-by: Geert Uytterhoeven <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>

commit b0ad20a upstream.

On the StarFive JH7100 RISC-V SoC the UART core clocks can't be set to
exactly 16 * 115200Hz and many other common bitrates. Trying this will
only result in a higher input clock, but low enough that the UART's
internal divisor can't come close enough to the baud rate target.
So rather than try to set the input clock it's better to skip the
clk_set_rate call and rely solely on the UART's internal divisor.

Reviewed-by: Andy Shevchenko <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>

commit ec85362 upstream.

Add initial device tree for the JH7100 RISC-V SoC by StarFive Ltd. This
is a test chip for their upcoming JH7110 SoC.

The CPU and cache data is based on the device tree in the vendor u-boot
port.

Acked-by: Palmer Dabbelt <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>

commit a436762 upstream.

Add initial device tree for the BeagleV Starlight Beta board. About 300
of these boards were sent out as part of a now cancelled BeagleBoard.org
project.

I2C timing data is based on the device tree in the vendor u-boot port.
Heartbeat LED added by Geert.

Acked-by: Palmer Dabbelt <[email protected]>
Co-developed-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>

commit 299e6f7 upstream.

We need to include linux/io-64-nonatomic-lo-hi.h or readq/writeq won't
be defined when compiling on 32bit architectures:

On i386:

../drivers/reset/reset-starfive-jh7100.c: In function ‘jh7100_reset_update’:
../drivers/reset/reset-starfive-jh7100.c:81:10: error: implicit declaration of function ‘readq’; did you mean ‘readl’? [-Werror=implicit-function-declaration]
  value = readq(reg_assert);
           ^~~~~
../drivers/reset/reset-starfive-jh7100.c:86:2: error: implicit declaration of function ‘writeq’; did you mean ‘writel’? [-Werror=implicit-function-declaration]
  writeq(value, reg_assert);
  ^~~~~~

On m68k:

drivers/reset/reset-starfive-jh7100.c:81:17: error: implicit declaration of function 'readq'; did you mean 'readb'? [-Werror=implicit-function-declaration]
drivers/reset/reset-starfive-jh7100.c:86:9: error: implicit declaration of function 'writeq'; did you mean 'writel'? [-Werror=implicit-function-declaration]
cc1: all warnings being treated as errors
make[3]: *** [scripts/Makefile.build:289: drivers/reset/reset-starfive-jh7100.o] Error 1
make[2]: *** [scripts/Makefile.build:572: drivers/reset] Error 2
make[1]: *** [Makefile:1969: drivers] Error 2
make: *** [Makefile:226: __sub-make] Error 2

Fixes: 0be3a15 ("reset: starfive-jh7100: Add StarFive JH7100 reset driver")
Reported-by: Randy Dunlap <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>
Link: https://lore.kernel.org/r/[email protected]'
Signed-off-by: Arnd Bergmann <[email protected]>

Introduce ARCH_DMA_MINALIGN to riscv arch.

Signed-off-by: Xianting Tian <[email protected]>

Write a C version of memcpy() which uses the biggest data size allowed,
without generating unaligned accesses.

The procedure is made of three steps:
First copy data one byte at time until the destination buffer is aligned
to a long boundary.
Then copy the data one long at time shifting the current and the next u8
to compose a long at every cycle.
Finally, copy the remainder one byte at time.

On a BeagleV, the TCP RX throughput increased by 45%:

before:

$ iperf3 -c beaglev
Connecting to host beaglev, port 5201
[  5] local 192.168.85.6 port 44840 connected to 192.168.85.48 port 5201
[ ID] Interval           Transfer     Bitrate         Retr  Cwnd
[  5]   0.00-1.00   sec  76.4 MBytes   641 Mbits/sec   27    624 KBytes
[  5]   1.00-2.00   sec  72.5 MBytes   608 Mbits/sec    0    708 KBytes
[  5]   2.00-3.00   sec  73.8 MBytes   619 Mbits/sec   10    451 KBytes
[  5]   3.00-4.00   sec  72.5 MBytes   608 Mbits/sec    0    564 KBytes
[  5]   4.00-5.00   sec  73.8 MBytes   619 Mbits/sec    0    658 KBytes
[  5]   5.00-6.00   sec  73.8 MBytes   619 Mbits/sec   14    522 KBytes
[  5]   6.00-7.00   sec  73.8 MBytes   619 Mbits/sec    0    621 KBytes
[  5]   7.00-8.00   sec  72.5 MBytes   608 Mbits/sec    0    706 KBytes
[  5]   8.00-9.00   sec  73.8 MBytes   619 Mbits/sec   20    580 KBytes
[  5]   9.00-10.00  sec  73.8 MBytes   619 Mbits/sec    0    672 KBytes
- - - - - - - - - - - - - - - - - - - - - - - - -
[ ID] Interval           Transfer     Bitrate         Retr
[  5]   0.00-10.00  sec   736 MBytes   618 Mbits/sec   71             sender
[  5]   0.00-10.01  sec   733 MBytes   615 Mbits/sec                  receiver

after:

$ iperf3 -c beaglev
Connecting to host beaglev, port 5201
[  5] local 192.168.85.6 port 44864 connected to 192.168.85.48 port 5201
[ ID] Interval           Transfer     Bitrate         Retr  Cwnd
[  5]   0.00-1.00   sec   109 MBytes   912 Mbits/sec   48    559 KBytes
[  5]   1.00-2.00   sec   108 MBytes   902 Mbits/sec    0    690 KBytes
[  5]   2.00-3.00   sec   106 MBytes   891 Mbits/sec   36    396 KBytes
[  5]   3.00-4.00   sec   108 MBytes   902 Mbits/sec    0    567 KBytes
[  5]   4.00-5.00   sec   106 MBytes   891 Mbits/sec    0    699 KBytes
[  5]   5.00-6.00   sec   106 MBytes   891 Mbits/sec   32    414 KBytes
[  5]   6.00-7.00   sec   106 MBytes   891 Mbits/sec    0    583 KBytes
[  5]   7.00-8.00   sec   106 MBytes   891 Mbits/sec    0    708 KBytes
[  5]   8.00-9.00   sec   106 MBytes   891 Mbits/sec   28    433 KBytes
[  5]   9.00-10.00  sec   108 MBytes   902 Mbits/sec    0    591 KBytes
- - - - - - - - - - - - - - - - - - - - - - - - -
[ ID] Interval           Transfer     Bitrate         Retr
[  5]   0.00-10.00  sec  1.04 GBytes   897 Mbits/sec  144             sender
[  5]   0.00-10.01  sec  1.04 GBytes   894 Mbits/sec                  receiver

And the decreased CPU time of the memcpy() is observable with perf top.
This is the `perf top -Ue task-clock` output when doing the test:

before:

Overhead  Shared O  Symbol
  42.22%  [kernel]  [k] memcpy
  35.00%  [kernel]  [k] __asm_copy_to_user
   3.50%  [kernel]  [k] sifive_l2_flush64_range
   2.30%  [kernel]  [k] stmmac_napi_poll_rx
   1.11%  [kernel]  [k] memset

after:

Overhead  Shared O  Symbol
  45.69%  [kernel]  [k] __asm_copy_to_user
  29.06%  [kernel]  [k] memcpy
   4.09%  [kernel]  [k] sifive_l2_flush64_range
   2.77%  [kernel]  [k] stmmac_napi_poll_rx
   1.24%  [kernel]  [k] memset

Signed-off-by: Matteo Croce <[email protected]>
Reported-by: kernel test robot <[email protected]>

When the destination buffer is before the source one, or when the
buffers doesn't overlap, it's safe to use memcpy() instead, which is
optimized to use a bigger data size possible.

Signed-off-by: Matteo Croce <[email protected]>
Reported-by: kernel test robot <[email protected]>

The generic memset is defined as a byte at time write. This is always
safe, but it's slower than a 4 byte or even 8 byte write.

Write a generic memset which fills the data one byte at time until the
destination is aligned, then fills using the largest size allowed,
and finally fills the remaining data one byte at time.

Signed-off-by: Matteo Croce <[email protected]>

The string library implements memset, memcpy and other library
functions, so tell the compiler not to optimise such code to just calls
to themselves.

This is correct for all compilers, but for some reason only Clang builds
break without this flag.

Signed-off-by: Emil Renner Berthing <[email protected]>

The problem is best illustrated by an example. Suppose a consumer wants
a 4MHz clock rate from a divider with a 10MHz parent. It would then
call

  clk_round_rate(clk, 4000000)

which would call into our determine_rate() callback that correctly
rounds up and finds that a divisor of 3 gives the highest possible
frequency below the requested 4MHz and returns 10000000 / 3 = 3333333Hz.

However the consumer would then call

  clk_set_rate(clk, 3333333)

but since 3333333 doesn't divide 10000000 evenly our set_rate() callback
would again round the divisor up and set it to 4 which results in an
unnecessarily low rate of 2.5MHz.

Fix it by using DIV_ROUND_CLOSEST in the set_rate() callback.

Signed-off-by: Emil Renner Berthing <[email protected]>

It turns out the audio_div clock is a fractional divider where the
lowest byte of the ctrl register is the integer part of the divider and
the 2nd byte is the number of 100th added to the divider.

The children of this clock is used by the audio peripherals for their
sample rate clock, so round to the closest possible rate rather than
always rounding down like regular dividers.

Signed-off-by: Emil Renner Berthing <[email protected]>

To improve human readability and enable automatic validation, the tuples
in the various properties containing interrupt specifiers should be
grouped.

Fix this by grouping the tuples of "interrupts-extended" properties
using angle brackets.

Signed-off-by: Geert Uytterhoeven <[email protected]>

Add all clock outputs for the StarFive JH7100 audio clock generator.

Signed-off-by: Emil Renner Berthing <[email protected]>

Add bindings for the audio clocks on the StarFive JH7100 RISC-V SoC.

Signed-off-by: Emil Renner Berthing <[email protected]>

The JH7100 has additional audio and video clocks at different memory
ranges, but they use the same register layout. Add a header and export
the starfive_jh7100_clk_ops function so the clock implementation can be
reused by drivers handling these clocks.

Signed-off-by: Emil Renner Berthing <[email protected]>

Unlike the system clocks there are audio clocks that combine both
multiplexer/divider and gate/multiplexer/divider, so add support for
that.

Signed-off-by: Emil Renner Berthing <[email protected]>

Add a driver for the audio clocks on the Starfive JH7100 RISC-V SoC.

Signed-off-by: Emil Renner Berthing <[email protected]>

Add device tree node for the audio clocks on the StarFive JH7100 RISC-V
SoC.

Signed-off-by: Emil Renner Berthing <[email protected]>

Add all resets for the StarFive JH7100 audio reset controller.

Signed-off-by: Emil Renner Berthing <[email protected]>

Add bindings for the audio reset controller on the StarFive JH7100
RISC-V SoC.

Signed-off-by: Emil Renner Berthing <[email protected]>

This moves the StarFive JH7100 reset driver to a new subdirectory in
preparation for adding more StarFive reset drivers.

Signed-off-by: Emil Renner Berthing <[email protected]>

The driver currently uses 64bit I/O on the 32bit registers. This works
because there are 4 assert registers and 4 status register, so they're
only ever accessed on 64bit boundaries.

There are however other reset controllers for audio and video on the SoC
with only one status register that isn't 64bit aligned so 64bit I/O
would result in an unaligned access exception.

Switch to 32bit I/O in preparation for supporting these resets too.

Signed-off-by: Emil Renner Berthing <[email protected]>

The audio resets are almost identical to the system resets, there are
just fewer of them. So factor out and export a generic probe function,
so most of the reset controller implementation can be shared.

Signed-off-by: Emil Renner Berthing <[email protected]>

Add device tree node for the audio resets on the StarFive JH7100 RISC-V
SoC.

Signed-off-by: Emil Renner Berthing <[email protected]>

Signed-off-by: Emil Renner Berthing <[email protected]>

Current u-boot doesn't seem to take into account that some GPIOs are
configured as inputs/outputs of certain peripherals on power-up. This
means it ends up configuring some GPIOs as inputs to more than one
peripheral which the documentation explicitly says is illegal. Similarly
it also ends up configuring more than one GPIO as output of the same
peripheral. While not explicitly mentioned by the documentation this
also seems like a bad idea.

The easiest way to remedy this mess is to just disconnect all GPIOs from
peripherals and have our pinmux configuration set everything up
properly. This, however, means that we'd disconnect the serial console
from its pins for a while, so add a device tree property to keep
certain GPIOs from being reset.

Signed-off-by: Emil Renner Berthing <[email protected]>

..rather than multiple calls to of_device_is_compatible().

Signed-off-by: Emil Renner Berthing <[email protected]>

This adds a compatible for the high speed UARTs on the StarFive JH7100
RISC-V SoC. Just like the regular uarts we also need to keep the input
clocks at their default rate and rely only on the divisor in the UART.

Signed-off-by: Emil Renner Berthing <[email protected]>

Add bindings for the temperature sensor on the StarFive JH7100 SoC.

Signed-off-by: Emil Renner Berthing <[email protected]>
Reviewed-by: Rob Herring <[email protected]>

Register definitions and conversion constants based on sfctemp driver by
Samin in the StarFive 5.10 kernel.

Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Samin Guo <[email protected]>

Signed-off-by: Samin Guo <[email protected]>
Signed-off-by: Walker Chen <[email protected]>

This makes it easier to find out which driver passes a wrong address
range.

Signed-off-by: Geert Uytterhoeven <[email protected]>

[Emil: fix suggested by Geert Uytterhoeven <[email protected]>]

Signed-off-by: Atish Patra <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>

Clear CNTR of PWM after setting period & duty_cycle

The first DMAC instance in the StarFive JH7100 SoC supports 16 DMA
channels.

FIXME Given there are more changes to the driver than just increasing
      DMAC_MAX_CHANNELS, we probably need a new compatible value, too.

Signed-off-by: Geert Uytterhoeven <[email protected]>

Found by comparing the parallel implementation of more than 8 channel
support for the StarFive JH7100 SoC by Samin.

Fixes: 8243516 ("dmaengine: dw-axi-dmac: support DMAX_NUM_CHANNELS > 8")
Co-developed-by: Samin Guo <[email protected]>
Signed-off-by: Samin Guo <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>

Signed-off-by: Samin Guo <[email protected]>
Signed-off-by: Curry Zhang <[email protected]>

Signed-off-by: Samin Guo <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>

iort_dma_setup() is being removed by commit db59e1b ("ACPI:
arm64: Move DMA setup operations out of IORT") in iommu/next:

    drivers/dma/dw-axi-dmac-starfive/starfive_dmaengine_memcpy.c: In function ‘dw_dma_async_
    do_memcpy’:
    drivers/dma/dw-axi-dmac-starfive/starfive_dmaengine_memcpy.c:152:2: error: implicit decl
    aration of function ‘iort_dma_setup’ [-Werror=implicit-function-declaration]
      152 |  iort_dma_setup(dma_dev, &dma_addr, &dma_size);
	  |  ^~~~~~~~~~~~~~
    drivers/dma/dw-axi-dmac-starfive/starfive_dmaengine_memcpy.c:153:8: warning: assignment to ‘const struct iommu_ops *’ from ‘int’ makes pointer from integer without a cast [-Wint-conversion]
      153 |  iommu = iort_iommu_configure_id(dma_dev, NULL);
	  |        ^
    drivers/dma/dw-axi-dmac-starfive/starfive_dmaengine_memcpy.c: In function ‘dw_dma_memcpy_raw’:
    drivers/dma/dw-axi-dmac-starfive/starfive_dmaengine_memcpy.c:223:8: warning: assignment to ‘const struct iommu_ops *’ from ‘int’ makes pointer from integer without a cast [-Wint-conversion]
      223 |  iommu = iort_iommu_configure_id(dma_dev, NULL);
	  |        ^

iort_dma_setup() and iort_iommu_configure_id() are part of the ARM64
ACPI implementation.  As CONFIG_ACPI_IORT cannot be enabled on RISC-V,
they were dummies anyway, so these calls can just be removed.

[Emil: remove unused local variables too]

Signed-off-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>
---
Boot-tested, but the affected code paths were not exercised.

Signed-off-by: Walker Chen <[email protected]>

Signed-off-by: Matteo Croce <[email protected]>

Signed-off-by: Michael Yan <[email protected]>
Signed-off-by: Jenny Zhang <[email protected]>
Signed-off-by: Walker Chen <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>

1. Add starfive DRM Display driver framework
2. Support M31 Phy and tda998x

Signed-off-by: jack.zhu <[email protected]>
Signed-off-by: keith.zhao <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>

A proper solution to this hack should be found.

Signed-off-by: jack.zhu <[email protected]>
Signed-off-by: keith.zhao <[email protected]>

Signed-off-by: Emil Renner Berthing <[email protected]>

Signed-off-by: Emil Renner Berthing <[email protected]>

Signed-off-by: Emil Renner Berthing <[email protected]>

Signed-off-by: Emil Renner Berthing <[email protected]>

When creating dumb buffers with 32bpp and 24bit colour depth this is
default mode return by drm_mode_legacy_fb_format. So we need to support
this for common dumb buffers to just work.

Signed-off-by: Emil Renner Berthing <[email protected]>

Signed-off-by: Emil Renner Berthing <[email protected]>

Additional update from Prashant Gaikwad <[email protected]>
Adapted for Linux 5.13 and the BeagleV Starlight board by
<[email protected]>

Signed-off-by: Emil Renner Berthing <[email protected]>

This IP is also used on the StarFive JH7100 riscv64 SoC and presumably
also the upcoming JH7110 SoC.

Signed-off-by: Emil Renner Berthing <[email protected]>

Signed-off-by: Emil Renner Berthing <[email protected]>

** Do not upstream **

This is hacky fix just for testing. The actual patch would read the
RISCV_UNCACHED_OFFSET from the DT for only the non-coherent devices.
All other devices on beagleV and all other platform should just set
dma_default_coherent to true.

[Emil: remove spurious whitespace and fix format string warning]

Signed-off-by: Atish Patra <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>

Based on the device tree in https://github.com/starfive-tech/u-boot/
with contributions from:
yanhong.wang <[email protected]>
Huan.Feng <[email protected]>
ke.zhu <[email protected]>
yiming.li <[email protected]>
jack.zhu <[email protected]>
Samin Guo <[email protected]>
Chenjieqin <[email protected]>
bo.li <[email protected]>

Rearranged, cleanups, fixes, pins and resets added by Emil.
Cleanups, fixes, clocks added by Geert.
Cleanups and GPIO fixes from Drew.
Thermal zone added by Stephen.
PWM pins added by Jianlong.

Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Stephen L Arnold <[email protected]>
Signed-off-by: Drew Fustini <[email protected]>
Signed-off-by: Jianlong Huang <[email protected]>

Signed-off-by: TekkamanV <[email protected]>

For convenience this also adds a small visionfive_defconfig and the
firmware needed for the brcmfmac driver along with the signed regulatory
database.

The firmware is from the linux-firmware repo and the regulatory database
from the wireless-regdb Fedora package.

Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Drew Fustini <[email protected]>

1, enable Sound Card as build-in, m to y
2, enable CONFIG_SOC_SIFIVE for fixing Oops/panic problem
3, expand CMA size to 32MB by CONFIG_CMA_SIZE_MBYTES=32

Signed-off-by: TekkamanV <[email protected]>