rm generics in PwmInput, Qei

CHANGELOG.md

@@ -9,7 +9,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Breaking changes
 
-- Relax pin type generics for `Serial`, `I2c`, `Spi`, `Can`. [#462]
+- Relax pin type generics for `Serial`, `I2c`, `Spi`, `Can`, `Qei`, `PwmInput`. [#462]
   ~~Use enums of pin tuples and `Enum::from<(tuple)>` for pin remap before passing to peripheral.~~
   Use pin enums and `impl RInto<(enum), R>` for peripheral constructors.
   Add `RInto` trait and `Rmp` peripheral wrapper, add `remap` for peripherals. [#514]
@@ -18,6 +18,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Take `&Clocks` instead of `Clocks` [#498]
 - Temporary replace `stm32f1` with `stm32f1-staging` [#503]
 - `Spi` now takes `Option<PIN>` for `SCK`, `MISO`, `MOSI` [#514]
+- move `Qei` mod inside `pwm_input` mod
 
 ### Changed
 

examples/pwm_input.rs

@@ -7,11 +7,7 @@
 use panic_halt as _;
 
 use cortex_m_rt::entry;
-use stm32f1xx_hal::{
-    pac,
-    prelude::*,
-    timer::{pwm_input::*, Timer},
-};
+use stm32f1xx_hal::{pac, prelude::*, timer::pwm_input::*};
 
 #[entry]
 fn main() -> ! {
@@ -31,11 +27,11 @@ fn main() -> ! {
     let (_pa15, _pb3, pb4) = afio.mapr.disable_jtag(gpioa.pa15, gpiob.pb3, gpiob.pb4);
     let pb5 = gpiob.pb5;
 
-    let pwm_input = Timer::new(p.TIM3, &clocks).pwm_input(
+    let pwm_input = p.TIM3.remap(&mut afio.mapr).pwm_input(
         (pb4, pb5),
-        &mut afio.mapr,
         &mut dbg,
         Configuration::Frequency(10.kHz()),
+        &clocks,
     );
 
     loop {

examples/qei.rs

@@ -9,7 +9,11 @@ use panic_semihosting as _;
 use cortex_m_semihosting::hprintln;
 
 use cortex_m_rt::entry;
-use stm32f1xx_hal::{pac, prelude::*, qei::QeiOptions, timer::Timer};
+use stm32f1xx_hal::{
+    pac,
+    prelude::*,
+    timer::{pwm_input::QeiOptions, Timer},
+};
 
 #[entry]
 fn main() -> ! {
@@ -21,8 +25,6 @@ fn main() -> ! {
 
     let clocks = rcc.cfgr.freeze(&mut flash.acr);
 
-    let mut afio = dp.AFIO.constrain();
-
     // let gpioa = dp.GPIOA.split();
     let gpiob = dp.GPIOB.split();
 
@@ -38,7 +40,7 @@ fn main() -> ! {
     let c1 = gpiob.pb6;
     let c2 = gpiob.pb7;
 
-    let qei = Timer::new(dp.TIM4, &clocks).qei((c1, c2), &mut afio.mapr, QeiOptions::default());
+    let qei = Timer::new(dp.TIM4, &clocks).qei((c1, c2), QeiOptions::default());
     let mut delay = cp.SYST.delay(&clocks);
 
     loop {

src/lib.rs

@@ -142,7 +142,6 @@ pub mod flash;
 pub mod gpio;
 pub mod i2c;
 pub mod prelude;
-pub mod qei;
 pub mod rcc;
 pub mod rtc;
 pub mod serial;

src/prelude.rs

@@ -20,6 +20,8 @@ pub use crate::rcc::RccExt as _stm32_hal_rcc_RccExt;
 pub use crate::serial::SerialExt as _;
 pub use crate::spi::SpiExt as _;
 pub use crate::time::U32Ext as _stm32_hal_time_U32Ext;
+pub use crate::timer::pwm_input::PwmInputExt as _;
+pub use crate::timer::pwm_input::QeiExt as _;
 #[cfg(feature = "rtic")]
 pub use crate::timer::MonoTimerExt as _stm32f4xx_hal_timer_MonoTimerExt;
 pub use crate::timer::PwmExt as _stm32f4xx_hal_timer_PwmExt;