rcc: access to Enable and Reset for owner only

src/adc.rs

@@ -271,15 +271,15 @@ macro_rules! adc_hal {
                 }
 
                 fn reset(&mut self) {
-                    <$ADC>::reset();
+                    self.rb.reset();
                 }
 
                 fn enable_clock(&mut self) {
-                    <$ADC>::enable();
+                    self.rb.enable();
                 }
 
                 fn disable_clock(&mut self) {
-                    <$ADC>::disable();
+                    self.rb.disable();
                 }
 
                 fn calibrate(&mut self) {

src/afio.rs

@@ -13,8 +13,8 @@ pub trait AfioExt {
 
 impl AfioExt for AFIO {
     fn constrain(self) -> Parts {
-        AFIO::enable();
-        AFIO::reset();
+        self.enable();
+        self.reset();
 
         Parts {
             evcr: EVCR { _0: () },

src/can.rs

@@ -95,7 +95,7 @@ where
     /// prevent accidental shared usage.
     #[cfg(not(feature = "connectivity"))]
     pub fn new(can: Instance, _usb: pac::USB) -> Can<Instance> {
-        Instance::enable();
+        can.enable();
 
         Can { _peripheral: can }
     }

src/crc.rs

@@ -12,7 +12,7 @@ pub trait CrcExt {
 
 impl CrcExt for CRC {
     fn new(self) -> Crc {
-        CRC::enable();
+        self.enable();
 
         Crc { crc: self }
     }

src/dma.rs

@@ -447,7 +447,7 @@ macro_rules! dma {
                     type Channels = Channels;
 
                     fn split(self) -> Channels {
-                        $DMAX::enable();
+                        self.enable();
 
                         // reset the DMA control registers (stops all on-going transfers)
                         $(

src/gpio.rs

@@ -366,8 +366,8 @@ macro_rules! gpio {
                 type Parts = Parts;
 
                 fn split(self) -> Parts {
-                    $GPIOX::enable();
-                    $GPIOX::reset();
+                    self.enable();
+                    self.reset();
 
                     Parts {
                         crl: Cr::<$port_id, false>(()),

src/i2c.rs

@@ -166,8 +166,8 @@ where
     /// Configures the I2C peripheral to work in master mode
     fn configure<M: Into<Mode>>(i2c: I2C, pins: PINS, mode: M, clocks: Clocks) -> Self {
         let mode = mode.into();
-        I2C::enable();
-        I2C::reset();
+        i2c.enable();
+        i2c.reset();
 
         let pclk1 = I2C::clock(&clocks);
 

src/rcc.rs

@@ -73,13 +73,6 @@ impl APB1 {
     }
 }
 
-impl APB1 {
-    /// Set power interface clock (PWREN) bit in RCC_APB1ENR
-    pub fn set_pwren() {
-        PWR::enable();
-    }
-}
-
 /// Advanced Peripheral Bus 2 (APB2) registers
 pub struct APB2 {
     _0: (),
@@ -308,8 +301,8 @@ impl BKP {
     /// Enables write access to the registers in the backup domain
     pub fn constrain(self, bkp: crate::pac::BKP, pwr: &mut PWR) -> BackupDomain {
         // Enable the backup interface by setting PWREN and BKPEN
-        crate::pac::BKP::enable();
-        crate::pac::PWR::enable();
+        bkp.enable();
+        pwr.enable();
 
         // Enable access to the backup registers
         pwr.cr.modify(|_r, w| w.dbp().set_bit());
@@ -468,12 +461,12 @@ pub trait RccBus: crate::Sealed {
 
 /// Enable/disable peripheral
 pub trait Enable: RccBus {
-    fn enable();
-    fn disable();
+    fn enable(&self);
+    fn disable(&self);
 }
 /// Reset peripheral
 pub trait Reset: RccBus {
-    fn reset();
+    fn reset(&self);
 }
 
 #[derive(Clone, Copy, Debug, PartialEq)]

src/rcc/enable.rs

@@ -11,14 +11,14 @@ macro_rules! bus {
             }
             impl Enable for crate::pac::$PER {
                 #[inline(always)]
-                fn enable() {
+                fn enable(&self) {
                     let rcc = unsafe { &(*RCC::ptr()) };
                     unsafe {
                         bb::set(Self::Bus::enr(rcc), $bit);
                     }
                 }
                 #[inline(always)]
-                fn disable() {
+                fn disable(&self) {
                     let rcc = unsafe { &(*RCC::ptr()) };
                     unsafe {
                         bb::clear(Self::Bus::enr(rcc), $bit);
@@ -27,7 +27,7 @@ macro_rules! bus {
             }
             impl Reset for crate::pac::$PER {
                 #[inline(always)]
-                fn reset() {
+                fn reset(&self) {
                     let rcc = unsafe { &(*RCC::ptr()) };
                     unsafe {
                         bb::set(Self::Bus::rstr(rcc), $bit);
@@ -49,14 +49,14 @@ macro_rules! ahb_bus {
             }
             impl Enable for crate::pac::$PER {
                 #[inline(always)]
-                fn enable() {
+                fn enable(&self) {
                     let rcc = unsafe { &(*RCC::ptr()) };
                     unsafe {
                         bb::set(Self::Bus::enr(rcc), $bit);
                     }
                 }
                 #[inline(always)]
-                fn disable() {
+                fn disable(&self) {
                     let rcc = unsafe { &(*RCC::ptr()) };
                     unsafe {
                         bb::clear(Self::Bus::enr(rcc), $bit);

src/serial.rs

@@ -292,8 +292,8 @@ impl<USART: Instance, PINS> Serial<USART, PINS> {
         PINS: Pins<USART>,
     {
         // Enable and reset USART
-        USART::enable();
-        USART::reset();
+        usart.enable();
+        usart.reset();
 
         PINS::remap(mapr);
 

src/spi.rs

@@ -468,8 +468,8 @@ where
 {
     fn configure(spi: SPI, pins: PINS, mode: Mode, freq: Hertz, clocks: Clocks) -> Self {
         // enable or reset SPI
-        SPI::enable();
-        SPI::reset();
+        spi.enable();
+        spi.reset();
 
         // disable SS output
         spi.cr2.write(|w| w.ssoe().clear_bit());
@@ -539,8 +539,8 @@ where
 {
     fn configure(spi: SPI, pins: PINS, mode: Mode) -> Self {
         // enable or reset SPI
-        SPI::enable();
-        SPI::reset();
+        spi.enable();
+        spi.reset();
 
         // disable SS output
         spi.cr2.write(|w| w.ssoe().clear_bit());

src/timer.rs

@@ -637,8 +637,8 @@ impl<TIM: Instance> Timer<TIM> {
     /// Initialize timer
     pub fn new(tim: TIM, clocks: &Clocks) -> Self {
         // Enable and reset the timer peripheral
-        TIM::enable();
-        TIM::reset();
+        tim.enable();
+        tim.reset();
 
         Self {
             clk: TIM::timer_clock(clocks),
@@ -710,8 +710,8 @@ impl<TIM: Instance, const FREQ: u32> FTimer<TIM, FREQ> {
     /// Initialize timer
     pub fn new(tim: TIM, clocks: &Clocks) -> Self {
         // Enable and reset the timer peripheral
-        TIM::enable();
-        TIM::reset();
+        tim.enable();
+        tim.reset();
 
         let mut t = Self { tim };
         t.configure(clocks);

src/usb.rs

@@ -28,10 +28,12 @@ unsafe impl UsbPeripheral for Peripheral {
     const EP_MEMORY_ACCESS_2X16: bool = false;
 
     fn enable() {
+        // TODO: use self.usb, after adding the &self parameter
+        let usb = unsafe { crate::pac::Peripherals::steal().USB };
         // Enable USB peripheral
-        USB::enable();
+        usb.enable();
         // Reset USB peripheral
-        USB::reset();
+        usb.reset();
     }
 
     fn startup_delay() {