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stm32f1-staging #503

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Oct 5, 2024
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stm32f1-staging #503

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1 change: 1 addition & 0 deletions CHANGELOG.md
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Expand Up @@ -14,6 +14,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
Remove `RemapStruct`s. [#462]
- Use independent `Spi` and `SpiSlave` structures instead of `OP` generic [#462]
- Take `&Clocks` instead of `Clocks` [#498]
- Temporary replace `stm32f1` with `stm32f1-staging`

### Changed

Expand Down
8 changes: 7 additions & 1 deletion Cargo.toml
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Expand Up @@ -21,7 +21,6 @@ default-target = "x86_64-unknown-linux-gnu"
cortex-m = "0.7.6"
cortex-m-rt = "0.7.1"
nb = "1.1"
stm32f1 = "0.15.1"
embedded-dma = "0.2.0"
bxcan = "0.7"
void = { default-features = false, version = "1.0.2" }
Expand All @@ -31,6 +30,11 @@ rtic-monotonic = { version = "1.0", optional = true }
bitflags = "1.3.2"
vcell = "0.1.3"

[dependencies.stm32f1]
package = "stm32f1-staging"
version = "0.16.0"
features = ["atomics"]

[dependencies.embedded-hal-02]
package = "embedded-hal"
version = "0.2.7"
Expand Down Expand Up @@ -68,6 +72,8 @@ stm32f103 = ["stm32f1/stm32f103", "has-can", "stm32-usbd"]
stm32f105 = ["stm32f1/stm32f107", "connectivity"]
stm32f107 = ["stm32f1/stm32f107", "connectivity"]

defmt = ["stm32f1/defmt"]

# Devices with 64 or 128 Kb ROM
medium = []
# Devices with 256 or 512 Kb ROM
Expand Down
6 changes: 3 additions & 3 deletions examples/blinky_rtcalarm_irq.rs
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Expand Up @@ -66,7 +66,7 @@ fn RTCALARM() {
cortex_m::interrupt::free(|cs| G_EXTI.borrow(cs).replace(None).unwrap())
});

exti.pr.write(|w| w.pr17().set_bit());
exti.pr().write(|w| w.pr17().clear_bit_by_one());
rtc.set_alarm(rtc.current_time() + TOGGLE_INTERVAL_SECONDS);

let _ = led.toggle();
Expand All @@ -89,8 +89,8 @@ fn main() -> ! {

// Set up the EXTI (see notes in section 18.4.2 of reference manual)
let exti = dp.EXTI;
exti.ftsr.write(|w| w.tr17().set_bit());
exti.imr.write(|w| w.mr17().set_bit());
exti.ftsr().write(|w| w.tr17().set_bit());
exti.imr().write(|w| w.mr17().set_bit());

cortex_m::interrupt::free(|cs| *G_EXTI.borrow(cs).borrow_mut() = Some(exti));

Expand Down
148 changes: 79 additions & 69 deletions src/adc.rs
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14 changes: 7 additions & 7 deletions src/afio.rs
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Expand Up @@ -57,7 +57,7 @@ pub struct EVCR {

impl EVCR {
pub fn evcr(&mut self) -> &afio::EVCR {
unsafe { &(*AFIO::ptr()).evcr }
unsafe { (*AFIO::ptr()).evcr() }
}
}

Expand All @@ -78,7 +78,7 @@ pub struct MAPR {

impl MAPR {
fn mapr(&mut self) -> &afio::MAPR {
unsafe { &(*AFIO::ptr()).mapr }
unsafe { (*AFIO::ptr()).mapr() }
}

pub fn modify_mapr<F>(&mut self, mod_fn: F)
Expand Down Expand Up @@ -117,7 +117,7 @@ pub struct EXTICR1 {

impl EXTICR1 {
pub fn exticr1(&mut self) -> &afio::EXTICR1 {
unsafe { &(*AFIO::ptr()).exticr1 }
unsafe { (*AFIO::ptr()).exticr1() }
}
}

Expand All @@ -127,7 +127,7 @@ pub struct EXTICR2 {

impl EXTICR2 {
pub fn exticr2(&mut self) -> &afio::EXTICR2 {
unsafe { &(*AFIO::ptr()).exticr2 }
unsafe { (*AFIO::ptr()).exticr2() }
}
}

Expand All @@ -137,7 +137,7 @@ pub struct EXTICR3 {

impl EXTICR3 {
pub fn exticr3(&mut self) -> &afio::EXTICR3 {
unsafe { &(*AFIO::ptr()).exticr3 }
unsafe { (*AFIO::ptr()).exticr3() }
}
}

Expand All @@ -147,7 +147,7 @@ pub struct EXTICR4 {

impl EXTICR4 {
pub fn exticr4(&mut self) -> &afio::EXTICR4 {
unsafe { &(*AFIO::ptr()).exticr4 }
unsafe { (*AFIO::ptr()).exticr4() }
}
}

Expand All @@ -157,6 +157,6 @@ pub struct MAPR2 {

impl MAPR2 {
pub fn mapr2(&mut self) -> &afio::MAPR2 {
unsafe { &(*AFIO::ptr()).mapr2 }
unsafe { (*AFIO::ptr()).mapr2() }
}
}
4 changes: 2 additions & 2 deletions src/backup_domain.rs
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Expand Up @@ -25,13 +25,13 @@ pub struct BackupDomain {

macro_rules! write_drx {
($self:ident, $drx:ident, $idx:expr, $new:expr) => {
$self._regs.$drx[$idx].write(|w| w.d().bits($new))
$self._regs.$drx($idx).write(|w| w.d().set($new))
};
}

macro_rules! read_drx {
($self:ident, $drx:ident, $idx:expr) => {
$self._regs.$drx[$idx].read().d().bits()
$self._regs.$drx($idx).read().d().bits()
};
}

Expand Down
6 changes: 3 additions & 3 deletions src/crc.rs
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Expand Up @@ -26,15 +26,15 @@ pub struct Crc {

impl Crc {
pub fn read(&self) -> u32 {
self.crc.dr.read().bits()
self.crc.dr().read().bits()
}

pub fn write(&mut self, val: u32) {
self.crc.dr.write(|w| w.dr().bits(val))
self.crc.dr().write(|w| w.dr().set(val))
}

pub fn reset(&self) {
self.crc.cr.write(|w| w.reset().set_bit());
self.crc.cr().write(|w| w.reset().set_bit());
// calling CRC::dr::write() just after CRC::cr::reset() will not work as expected, and
// inserting single nop() seems to solve the problem.
cortex_m::asm::nop();
Expand Down
6 changes: 3 additions & 3 deletions src/dac.rs
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Expand Up @@ -66,19 +66,19 @@ macro_rules! dac {
impl DacPin for $CX {
fn enable(&mut self) {
let dac = unsafe { &(*DAC::ptr()) };
dac.cr.modify(|_, w| w.$en().set_bit());
dac.cr().modify(|_, w| w.$en().set_bit());
}
}

impl DacOut<u16> for $CX {
fn set_value(&mut self, val: u16) {
let dac = unsafe { &(*DAC::ptr()) };
dac.$dhrx.write(|w| unsafe { w.bits(val as u32) });
dac.$dhrx().write(|w| unsafe { w.bits(val as u32) });
}

fn get_value(&mut self) -> u16 {
let dac = unsafe { &(*DAC::ptr()) };
dac.$dac_dor.read().bits() as u16
dac.$dac_dor().read().bits() as u16
}
}
};
Expand Down
32 changes: 16 additions & 16 deletions src/dma.rs
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Expand Up @@ -144,32 +144,32 @@ macro_rules! dma {
///
/// `inc` indicates whether the address will be incremented after every byte transfer
pub fn set_peripheral_address(&mut self, address: u32, inc: bool) {
self.ch().par.write(|w| unsafe { w.pa().bits(address) } );
self.ch().cr.modify(|_, w| w.pinc().bit(inc) );
self.ch().par().write(|w| unsafe { w.pa().bits(address) } );
self.ch().cr().modify(|_, w| w.pinc().bit(inc) );
}

/// `address` where from/to data will be read/write
///
/// `inc` indicates whether the address will be incremented after every byte transfer
pub fn set_memory_address(&mut self, address: u32, inc: bool) {
self.ch().mar.write(|w| unsafe { w.ma().bits(address) } );
self.ch().cr.modify(|_, w| w.minc().bit(inc) );
self.ch().mar().write(|w| unsafe { w.ma().bits(address) } );
self.ch().cr().modify(|_, w| w.minc().bit(inc) );
}

/// Number of bytes to transfer
pub fn set_transfer_length(&mut self, len: usize) {
self.ch().ndtr.write(|w| w.ndt().bits(u16::try_from(len).unwrap()));
self.ch().ndtr().write(|w| w.ndt().set(u16::try_from(len).unwrap()));
}

/// Starts the DMA transfer
pub fn start(&mut self) {
self.ch().cr.modify(|_, w| w.en().set_bit() );
self.ch().cr().modify(|_, w| w.en().set_bit() );
}

/// Stops the DMA transfer
pub fn stop(&mut self) {
self.ifcr().write(|w| w.$cgifX().set_bit());
self.ch().cr.modify(|_, w| w.en().clear_bit() );
self.ch().cr().modify(|_, w| w.en().clear_bit() );
}

/// Returns `true` if there's a transfer in progress
Expand All @@ -181,40 +181,40 @@ macro_rules! dma {
impl $CX {
pub fn listen(&mut self, event: Event) {
match event {
Event::HalfTransfer => self.ch().cr.modify(|_, w| w.htie().set_bit()),
Event::HalfTransfer => self.ch().cr().modify(|_, w| w.htie().set_bit()),
Event::TransferComplete => {
self.ch().cr.modify(|_, w| w.tcie().set_bit())
self.ch().cr().modify(|_, w| w.tcie().set_bit())
}
}
}

pub fn unlisten(&mut self, event: Event) {
match event {
Event::HalfTransfer => {
self.ch().cr.modify(|_, w| w.htie().clear_bit())
self.ch().cr().modify(|_, w| w.htie().clear_bit())
},
Event::TransferComplete => {
self.ch().cr.modify(|_, w| w.tcie().clear_bit())
self.ch().cr().modify(|_, w| w.tcie().clear_bit())
}
}
}

pub fn ch(&mut self) -> &dma1::CH {
unsafe { &(*$DMAX::ptr()).$chX }
unsafe { (*$DMAX::ptr()).$chX() }
}

pub fn isr(&self) -> dma1::isr::R {
// NOTE(unsafe) atomic read with no side effects
unsafe { (*$DMAX::ptr()).isr.read() }
unsafe { (*$DMAX::ptr()).isr().read() }
}

pub fn ifcr(&self) -> &dma1::IFCR {
unsafe { &(*$DMAX::ptr()).ifcr }
unsafe { &(*$DMAX::ptr()).ifcr() }
}

pub fn get_ndtr(&self) -> u32 {
// NOTE(unsafe) atomic read with no side effects
unsafe { &(*$DMAX::ptr())}.$chX.ndtr.read().bits()
unsafe { &(*$DMAX::ptr())}.$chX().ndtr().read().bits()
}
}

Expand Down Expand Up @@ -453,7 +453,7 @@ macro_rules! dma {

// reset the DMA control registers (stops all on-going transfers)
$(
self.$chX.cr.reset();
self.$chX().cr().reset();
)+

Channels((), $($CX { _0: () }),+)
Expand Down
16 changes: 8 additions & 8 deletions src/flash.rs
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Expand Up @@ -367,7 +367,7 @@ pub struct ACR {
impl ACR {
pub(crate) fn acr(&mut self) -> &flash::ACR {
// NOTE(unsafe) this proxy grants exclusive access to this register
unsafe { &(*FLASH::ptr()).acr }
unsafe { (*FLASH::ptr()).acr() }
}
}

Expand All @@ -380,7 +380,7 @@ pub struct AR {
impl AR {
pub(crate) fn ar(&mut self) -> &flash::AR {
// NOTE(unsafe) this proxy grants exclusive access to this register
unsafe { &(*FLASH::ptr()).ar }
unsafe { (*FLASH::ptr()).ar() }
}
}

Expand All @@ -393,7 +393,7 @@ pub struct CR {
impl CR {
pub(crate) fn cr(&mut self) -> &flash::CR {
// NOTE(unsafe) this proxy grants exclusive access to this register
unsafe { &(*FLASH::ptr()).cr }
unsafe { (*FLASH::ptr()).cr() }
}
}

Expand All @@ -406,7 +406,7 @@ pub struct KEYR {
impl KEYR {
pub(crate) fn keyr(&mut self) -> &flash::KEYR {
// NOTE(unsafe) this proxy grants exclusive access to this register
unsafe { &(*FLASH::ptr()).keyr }
unsafe { (*FLASH::ptr()).keyr() }
}
}

Expand All @@ -419,7 +419,7 @@ pub struct OBR {
impl OBR {
pub(crate) fn obr(&mut self) -> &flash::OBR {
// NOTE(unsafe) this proxy grants exclusive access to this register
unsafe { &(*FLASH::ptr()).obr }
unsafe { (*FLASH::ptr()).obr() }
}
}

Expand All @@ -432,7 +432,7 @@ pub struct OPTKEYR {
impl OPTKEYR {
pub(crate) fn optkeyr(&mut self) -> &flash::OPTKEYR {
// NOTE(unsafe) this proxy grants exclusive access to this register
unsafe { &(*FLASH::ptr()).optkeyr }
unsafe { (*FLASH::ptr()).optkeyr() }
}
}

Expand All @@ -445,7 +445,7 @@ pub struct SR {
impl SR {
pub(crate) fn sr(&mut self) -> &flash::SR {
// NOTE(unsafe) this proxy grants exclusive access to this register
unsafe { &(*FLASH::ptr()).sr }
unsafe { (*FLASH::ptr()).sr() }
}
}

Expand All @@ -458,6 +458,6 @@ pub struct WRPR {
impl WRPR {
pub(crate) fn wrpr(&mut self) -> &flash::WRPR {
// NOTE(unsafe) this proxy grants exclusive access to this register
unsafe { &(*FLASH::ptr()).wrpr }
unsafe { (*FLASH::ptr()).wrpr() }
}
}
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