Rename insn access fault to fetch fault (riscv#380)

Fixes riscv#374 --------- Co-authored-by: Tariq Kurd <[email protected]>
tariqkurd-repo · Oct 9, 2024 · b9d6f6e · b9d6f6e
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Showing 5 changed files with 5 additions and 5 deletions.
diff --git a/src/debug-integration.adoc b/src/debug-integration.adoc
@@ -115,7 +115,7 @@ for details.
 As a result, the value of <<pcc>> is UNSPECIFIED in debug mode according
 to this specification. The <<pcc>> metadata has no architectural effect in debug
 mode. Therefore <<asr_perm>> is implicitly granted for access to all CSRs and
-no PCC faults are possible.
+no CHERI instruction fetch faults are possible.
 
 <<dpcc>> (and consequently <<dpc>>) are updated with the
 capability in <<pcc>> whose address field is set to the address of the next

diff --git a/src/insns/mret_sret.adoc b/src/insns/mret_sret.adoc
@@ -26,7 +26,7 @@ result into <<pcc>>. SRET unseals <<sepcc>> and writes the result into <<pcc>>.
 Exceptions::
 CHERI fault exceptions occur when <<pcc>> does not grant <<asr_perm>> because
 <<MRET>> and <<SRET>> require access to privileged CSRs. When that exception
-occurs, _CHERI instruction access fault_ is reported in the TYPE field and the
+occurs, _CHERI instruction fetch fault_ is reported in the TYPE field and the
 Permission violation code is reported in the CAUSE field of <<mtval>> or
 <<stval>>.
 

diff --git a/src/insns/zcmt_cmjalt.adoc b/src/insns/zcmt_cmjalt.adoc
@@ -39,7 +39,7 @@ include::zcm_common.adoc[]
 Requires <<jvtc>> to be tagged, not sealed, have <<x_perm>> and for the full XLEN-wide access to be in <<jvtc>> bounds.
 
 {cheri_cap_mode_name} Exceptions::
-When these instructions cause CHERI exceptions, _CHERI instruction access fault_
+When these instructions cause CHERI exceptions, _CHERI instruction fetch fault_
 is reported in the TYPE field and the following codes may be
 reported in the CAUSE field of <<mtval>> or <<stval>>:
 

diff --git a/src/insns/zcmt_cmjt.adoc b/src/insns/zcmt_cmjt.adoc
@@ -39,7 +39,7 @@ include::zcm_common.adoc[]
 Requires <<jvtc>> to be tagged, not sealed, have <<x_perm>> and for the full XLEN-wide access to be in <<jvtc>> bounds.
 
 {cheri_cap_mode_name} Exceptions::
-When these instructions cause CHERI exceptions, _CHERI instruction access fault_
+When these instructions cause CHERI exceptions, _CHERI instruction fetch fault_
 is reported in the TYPE field and the following codes may be
 reported in the CAUSE field of <<mtval>> or <<stval>>:
 

diff --git a/src/riscv-integration.adoc b/src/riscv-integration.adoc
@@ -765,7 +765,7 @@ xref:mtval-cheri-causes[xrefstyle=short] respectively.
 [#mtval-cheri-type,width=65%,float="center",align="center",options=header,cols="30%,70%"]
 |==============================================================================
 | CHERI Type Code           | Description
-| {cheri_excep_type_pcc}    | CHERI instruction access fault
+| {cheri_excep_type_pcc}    | CHERI instruction fetch fault
 | {cheri_excep_type_data}   | CHERI data fault due to load, store or AMO
 | {cheri_excep_type_jump}   | CHERI jump or branch fault
 | 3-15                      | Reserved