- X86 Lea Expansion (WIP)

tgiphil · Nov 12, 2023 · 8cb2810 · 8cb2810
1 parent abf90bb
commit 8cb2810
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Showing 4 changed files with 40 additions and 4 deletions.
diff --git a/Source/Data/X86-Instructions.json b/Source/Data/X86-Instructions.json
@@ -1,7 +1,6 @@
 {
 	"Encoding": [
 		"[x86]=[instruction-prefix]|[address-prefix]|[operand-prefix]|[opcode]|[opcode2]|[opcode3]|[opcode4]|[mod]|[reg]|[rm]|[scale]|[index]|[base]|[displacement]|[immediate]",
-		"[x64]=[instruction-prefix]|[address-prefix]|[operand-prefix]|[rex.opcode]|[rex.w]|[rex.r]|[rex.x]|[rex.b]|[opcode]|[opcode2]|[opcode3]|[opcode4]|[mod]|[reg]|[rm]|[scale]|[index]|[base]|[displacement]|[immediate]",
 
 		"[x86-vex-3]=[vex.opcode]|[vex.R]|[vex.X]|[vex.B]|[vex.MapSelect]|[vex.WE]|[vex.vvvv]|[vex.L]|[vex.PP]|[vex.opcode2]|[mod]|[reg]|[rm],vex.opcode=0xC4,vex.R=1,vex.X=1,vex.B=1,vex.WE=0,vex.L=0,vex.PP=00",
 
@@ -1075,15 +1074,15 @@
 				},
 				{
 					"Condition": "[register][register][constant_1to4][zero]",
-					"Encoding": "[todo]"
+					"Encoding": "[x86],mod=00,reg=reg3:r,rm=100,scale=imm2scale:o3,index=reg3:o2,base=reg3:o2"
 				},
 				{
 					"Condition": "[register][register][constant_1to4][constant_imm8]",
-					"Encoding": "[todo]"
+					"Encoding": "[x86],mod=01,reg=reg3:r,rm=100,scale=imm2scale:o3,index=reg3:o2,base=reg3:o2,immediate=imm8:o4"
 				},
 				{
 					"Condition": "[register][register][constant_1to4][constant]",
-					"Encoding": "[todo]"
+					"Encoding": "[x86],mod=10,reg=reg3:r,rm=100,scale=imm2scale:o3,index=reg3:o2,base=reg3:o2,immediate=imm32:o4"
 				}
 			]
 		},

diff --git a/Source/Mosa.Compiler.Framework/OpcodeEncoder.cs b/Source/Mosa.Compiler.Framework/OpcodeEncoder.cs
@@ -239,6 +239,19 @@ public void Append64BitImmediate(ulong value)
 		AppendByte((byte)(value >> 56));
 	}
 
+	public void Append2BitSScale(Operand operand)
+	{
+		var v = operand.ConstantUnsigned32;
+
+		switch (v)
+		{
+			case 1: Append2Bits(0); return;
+			case 2: Append2Bits(1); return;
+			case 4: Append2Bits(2); return;
+			case 8: Append2Bits(3); return;
+		}
+	}
+
 	public void Append32BitImmediateWithOffset(Operand operand, Operand offset)
 	{
 		Debug.Assert(operand.IsConstant);

diff --git a/Source/Mosa.Compiler.x86/Instructions/Lea32.cs b/Source/Mosa.Compiler.x86/Instructions/Lea32.cs
@@ -110,16 +110,39 @@ public override void Emit(Node node, OpcodeEncoder opcodeEncoder)
 
 		if (node.Operand1.IsPhysicalRegister && node.Operand2.IsPhysicalRegister && node.Operand3.IsConstant && node.Operand3.ConstantUnsigned32 >= 1 && node.Operand3.ConstantUnsigned32 <= 4 && node.Operand4.IsConstantZero)
 		{
+			opcodeEncoder.Append8Bits(0x8D);
+			opcodeEncoder.Append2Bits(0b00);
+			opcodeEncoder.Append3Bits(node.Result.Register.RegisterCode);
+			opcodeEncoder.Append3Bits(0b100);
+			opcodeEncoder.Append2BitSScale(node.Operand3);
+			opcodeEncoder.Append3Bits(node.Operand2.Register.RegisterCode);
+			opcodeEncoder.Append3Bits(node.Operand2.Register.RegisterCode);
 			return;
 		}
 
 		if (node.Operand1.IsPhysicalRegister && node.Operand2.IsPhysicalRegister && node.Operand3.IsConstant && node.Operand3.ConstantUnsigned32 >= 1 && node.Operand3.ConstantUnsigned32 <= 4 && node.Operand4.IsConstant && node.Operand4.ConstantSigned32 >= -128 && node.Operand4.ConstantSigned32 <= 127)
 		{
+			opcodeEncoder.Append8Bits(0x8D);
+			opcodeEncoder.Append2Bits(0b01);
+			opcodeEncoder.Append3Bits(node.Result.Register.RegisterCode);
+			opcodeEncoder.Append3Bits(0b100);
+			opcodeEncoder.Append2BitSScale(node.Operand3);
+			opcodeEncoder.Append3Bits(node.Operand2.Register.RegisterCode);
+			opcodeEncoder.Append3Bits(node.Operand2.Register.RegisterCode);
+			opcodeEncoder.Append8BitImmediate(node.Operand4);
 			return;
 		}
 
 		if (node.Operand1.IsPhysicalRegister && node.Operand2.IsPhysicalRegister && node.Operand3.IsConstant && node.Operand3.ConstantUnsigned32 >= 1 && node.Operand3.ConstantUnsigned32 <= 4 && node.Operand4.IsConstant)
 		{
+			opcodeEncoder.Append8Bits(0x8D);
+			opcodeEncoder.Append2Bits(0b10);
+			opcodeEncoder.Append3Bits(node.Result.Register.RegisterCode);
+			opcodeEncoder.Append3Bits(0b100);
+			opcodeEncoder.Append2BitSScale(node.Operand3);
+			opcodeEncoder.Append3Bits(node.Operand2.Register.RegisterCode);
+			opcodeEncoder.Append3Bits(node.Operand2.Register.RegisterCode);
+			opcodeEncoder.Append32BitImmediate(node.Operand4);
 			return;
 		}
 

diff --git a/Source/Mosa.Utility.SourceCodeGenerator/BuildCommonInstructionFiles.cs b/Source/Mosa.Utility.SourceCodeGenerator/BuildCommonInstructionFiles.cs
@@ -834,6 +834,7 @@ private static void GetCodes(string part, ref string code, ref string postcode)
 			case "reg3s1": code = "Append3Bits"; postcode = ".Register.RegisterCode >> 1"; return;
 			case "imm1": code = "Append1BitImmediate"; return;
 			case "imm2": code = "Append2BitImmediate"; return;
+			case "imm2scale": code = "Append2BitSScale"; return;
 			case "imm4": code = "Append4BitImmediate"; return;
 			case "imm4hn": code = "Append4BitImmediateHighNibble"; return;
 			case "imm5": code = "Append5BitImmediate"; return;