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Capture simulator output and forward to logger (#76)
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Co-authored-by: Colin Marquardt <[email protected]>
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themperek and cmarqu authored Mar 20, 2020
1 parent 8c22eb6 commit 66d17ea
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Showing 3 changed files with 33 additions and 22 deletions.
6 changes: 5 additions & 1 deletion cocotb_test/run.py
Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
import os
import inspect
import shutil
import sys

import cocotb_test.simulator

Expand Down Expand Up @@ -40,8 +41,11 @@ def run(simulator=None, **kwargs):

results_xml_file = sim.run()

sys.tracebacklimit = 0 # remove not needed traceback from assert

if not kwargs.get("compile_only", False):
assert os.path.isfile(results_xml_file), "Simulation terminated abnormally. Results file not found."
results_file_exist = os.path.isfile(results_xml_file)
assert results_file_exist, "Simulation terminated abnormally. Results file not found."

tree = ET.parse(results_xml_file)
for ts in tree.iter("testsuite"):
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48 changes: 28 additions & 20 deletions cocotb_test/simulator.py
Original file line number Diff line number Diff line change
Expand Up @@ -6,6 +6,7 @@
import tempfile
import re
import cocotb
import logging

from distutils.spawn import find_executable

Expand Down Expand Up @@ -59,6 +60,10 @@ def __init__(

self.sim_name = sim_name

self.logger = logging.getLogger(sim_name)
self.logger.setLevel(logging.INFO)
logging.basicConfig(format='%(levelname)s %(name)s: %(message)s')

libs_dir = os.path.join(os.path.dirname(__file__), "libs")
self.lib_dir = os.path.join(libs_dir, sim_name)

Expand Down Expand Up @@ -210,29 +215,32 @@ def get_abs_paths(self, paths):

return paths_abs

def execute_log(self, cmds):
def execute(self, cmds):
self.set_env()
for cmd in cmds:
print(" ".join(cmd))

output_log = ""
process = subprocess.Popen(cmd, stdout=subprocess.PIPE, cwd=self.work_dir, env=self.env)
self.logger.info("Running command: "+" ".join(cmd))
process = subprocess.Popen(cmd, stdout=subprocess.PIPE, stderr=subprocess.STDOUT, cwd=self.work_dir, env=self.env)

while True:
out = process.stdout.read(1)
out = process.stdout.readline()

if not out and process.poll() != None:
break
if out != "":
output_log += out.decode("utf-8")
sys.stdout.write(out.decode("utf-8"))
sys.stdout.flush()

log_out = out.decode("utf-8").rstrip()
if log_out != "":
self.logger.info(log_out)

return output_log
if process.returncode:
self.logger.error("Command terminated with error %d" % process.returncode)
return

def execute(self, cmds):
self.set_env()
for cmd in cmds:
print(" ".join(cmd))
process = subprocess.check_call(cmd, cwd=self.work_dir, env=self.env)
# def execute(self, cmds):
# self.set_env()
# for cmd in cmds:
# print(" ".join(cmd))
# process = subprocess.check_call(cmd, cwd=self.work_dir, env=self.env)

def outdated(self, output, dependencies):

Expand Down Expand Up @@ -299,7 +307,7 @@ def build_command(self):
if self.outdated(self.sim_file, self.verilog_sources) or self.force_compile:
cmd.append(self.compile_command())
else:
print("Skipping compilation:" + self.sim_file)
self.logger.warning("Skipping compilation:" + self.sim_file)

# TODO: check dependency?
if not self.compile_only:
Expand Down Expand Up @@ -354,7 +362,7 @@ def build_command(self):
cmd.append(["vsim"] + ["-c"] + ["-do"] + [do_script])

else:
print("Skipping compilation:" + out_file)
self.logger.warning("Skipping compilation:" + out_file)

if not self.compile_only:
if self.toplevel_lang == "vhdl":
Expand Down Expand Up @@ -442,7 +450,7 @@ def build_command(self):
cmd.append(cmd_elab)

else:
print("Skipping compilation:" + out_file)
self.logger.warning("Skipping compilation:" + out_file)

if not self.compile_only:
cmd_run = ["irun", "-64", "-R", ("-gui" if self.gui else "")]
Expand Down Expand Up @@ -587,7 +595,7 @@ def build_command(self):
EXTRA_ARGS=" ".join(as_tcl_value(v) for v in self.compile_args),
)
else:
print("Skipping compilation:" + out_file)
self.logger.warning("Skipping compilation:" + out_file)

if not self.compile_only:
if self.toplevel_lang == "vhdl":
Expand Down
1 change: 0 additions & 1 deletion tests/test_dff.py
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,6 @@
import pytest
import os


@pytest.mark.skipif(os.getenv("SIM") == "ghdl", reason="Verilog not suported")
#@pytest.mark.parametrize("seed", range(10))
def test_dff_verilog():
Expand Down

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