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@@ -21,7 +21,7 @@ def read_file(fname): | |
author="Tomasz Hemperek", | ||
author_email="[email protected]", | ||
packages=find_packages(), | ||
install_requires=["cocotb==1.4.*", "pytest"], | ||
install_requires=["cocotb>=1.5", "pytest"], | ||
entry_points={ | ||
"console_scripts": [ | ||
"cocotb=cocotb_test.cli:config", | ||
|
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@@ -1,40 +1,15 @@ | ||
// ============================================================================= | ||
// Authors: Martin Zabel | ||
// | ||
// Module: A simple D-FF | ||
// | ||
// Description: | ||
// ------------------------------------ | ||
// A simple D-FF with an initial state of '0'. | ||
// | ||
// License: | ||
// ============================================================================= | ||
// Copyright 2016 Technische Universitaet Dresden - Germany | ||
// Chair for VLSI-Design, Diagnostics and Architecture | ||
// | ||
// Licensed under the Apache License, Version 2.0 (the "License"); | ||
// you may not use this file except in compliance with the License. | ||
// You may obtain a copy of the License at | ||
// | ||
// http://www.apache.org/licenses/LICENSE-2.0 | ||
// | ||
// Unless required by applicable law or agreed to in writing, software | ||
// distributed under the License is distributed on an "AS IS" BASIS, | ||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
// See the License for the specific language governing permissions and | ||
// limitations under the License. | ||
// ============================================================================= | ||
// This file is public domain, it can be freely copied without restrictions. | ||
// SPDX-License-Identifier: CC0-1.0 | ||
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`timescale 1us/1us | ||
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module dff_test (c,d,q); | ||
input wire c, d; | ||
output reg q = 1'b0; | ||
module dff_test ( | ||
input logic clk, d, | ||
output logic q | ||
); | ||
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always @(posedge clk) begin | ||
q <= d; | ||
end | ||
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always @(posedge c) | ||
begin | ||
// It is also possible to add an delay of less than one clock period | ||
// here. | ||
q <= d; | ||
end | ||
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endmodule // dff | ||
endmodule |
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-- ============================================================================= | ||
-- Authors: Martin Zabel | ||
-- | ||
-- Module: A simple D-FF | ||
-- | ||
-- Description: | ||
-- ------------------------------------ | ||
-- A simple D-FF with an initial state of '0'. | ||
-- | ||
-- License: | ||
-- ============================================================================= | ||
-- Copyright 2016 Technische Universitaet Dresden - Germany | ||
-- Chair for VLSI-Design, Diagnostics and Architecture | ||
-- | ||
-- Licensed under the Apache License, Version 2.0 (the "License"); | ||
-- you may not use this file except in compliance with the License. | ||
-- You may obtain a copy of the License at | ||
-- | ||
-- http://www.apache.org/licenses/LICENSE-2.0 | ||
-- | ||
-- Unless required by applicable law or agreed to in writing, software | ||
-- distributed under the License is distributed on an "AS IS" BASIS, | ||
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
-- See the License for the specific language governing permissions and | ||
-- limitations under the License. | ||
-- ============================================================================= | ||
-- This file is public domain, it can be freely copied without restrictions. | ||
-- SPDX-License-Identifier: CC0-1.0 | ||
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library ieee; | ||
use ieee.std_logic_1164.all; | ||
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entity dff_test_vhdl is | ||
port ( | ||
c : in std_logic; | ||
d : in std_logic; | ||
q : out std_logic := '0'); | ||
end entity dff_test_vhdl; | ||
port( | ||
clk: in std_logic; | ||
d: in std_logic; | ||
q: out std_logic); | ||
end dff_test_vhdl; | ||
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architecture rtl of dff_test_vhdl is | ||
architecture behavioral of dff_test_vhdl is | ||
begin | ||
-- It is also possible to add an delay of less than one clock period here. | ||
q <= d when rising_edge(c); | ||
end architecture rtl; | ||
process (clk) begin | ||
if rising_edge(clk) then | ||
q <= d; | ||
end if; | ||
end process; | ||
end behavioral; |
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