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ASoC: SOF: Intel: hda-sdw-bpt: add CHAIN_DMA support
When the firmware is involved, the data can be transferred with a CHAIN_DMA on LNL+. The CHAIN_DMA needs to be programmed before the DMAs per the documentation. The states are not exactly symmetrical, on stop we must do a PAUSE and RESET. The FIFO size of 10ms was determined experimentally. With the minimum of 2ms, errors were reported by the codec, likely because of xruns. The code flow deals with the two TX and RX CHAIN_DMAs in symmetrical ways, i.e. alloc TX alloc RX enable TX enable RX disable RX disable TX free RX free TX Signed-off-by: Pierre-Louis Bossart <[email protected]> Signed-off-by: Bard Liao <[email protected]>
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