icm40609d: Clear interrupt status at FIFO reset

If DRDY signal is used, the interrupt status needs to be cleared at FIFO reset
in order to make DRDY go back inactive. Otherwise there won't be a falling edge
interrupt at the next sample.

Signed-off-by: Jukka Laitinen <[email protected]>

src/drivers/imu/invensense/icm40609d/ICM40609D.cpp

@@ -599,6 +599,9 @@ void ICM40609D::FIFOReset()
 	// SIGNAL_PATH_RESET: FIFO flush
 	RegisterSetBits(Register::BANK_0::SIGNAL_PATH_RESET, SIGNAL_PATH_RESET_BIT::FIFO_FLUSH);
 
+	// Read INT_STATUS to clear
+	RegisterRead(Register::BANK_0::INT_STATUS);
+
 	// reset while FIFO is disabled
 	_drdy_timestamp_sample.store(0);
 }