Move resync flag to bit 14 of each DAC channel

src/fpga/hdl/sequence_slice.v

@@ -42,8 +42,9 @@ assign pdm_value_3[10:0] = seq_data_int[90:80];
 // Flags
 assign enable_dac[1:0] = seq_data_int[97:96];
 assign enable_pdm[3:0] = seq_data_int[101:98];
-assign resync_dac[1:0] = seq_data_int[31:30];
+assign resync_dac[0] = seq_data_int[14];
+assign resync_dac[1] = seq_data_int[30];
 assign enable_dac_ramp_down[0] = seq_data_int[112];
 assign enable_dac_ramp_down[1] = seq_data_int[113];
 
-endmodule
+endmodule

src/lib/rp-daq-lib.c

@@ -652,9 +652,9 @@ int setResyncDAC(int8_t value, int channel, int index) {
 	if (value < 0 || value >= 2)
 		return -1;
 
-	int bitpos = 14 + channel;
-	// Reset bits are in the 2nd channel -> bitpos 31:30
-	int offset = 8 * index + 1;
+	int bitpos = 14;
+	// Reset bits are in the 14th bit of the respective DAC channel -> 14 and 30 
+	int offset = 8 * index + channel;
 	// clear the bit
 	*((int16_t *)(pdm_cfg + offset)) &= ~(1u << bitpos);
 	// set the bit