Direct instantiation

A digital system is often composed of several smaller blocks. VHDL provides a mechanism how to build a larger system from simpler or predesigned components. It is called an instantiation. The syntax of direct instantiation is

<unit_label> : entity <lib_name>.<entity_name> (<arch_name>)
    generic map(
        <generic_name> => <default_value>,
        <other generics>...    
    )
    port map(
        <entity_signal> => <actual_signal>,
        <entity_signal> => <actual_signal>,
        <other signals>...
    );

where unit_label gives a unique ID for an instance, lib_name indicates in which library the component is defined, and entity_name and arch_name terms indicate names of entity and architecture. Note, architecture name is optional.

Let 1-of-4 decoder entity is defined in one_of_four.vhd source file as follows

entity one_of_four is
    port(
        a_i : in  std_logic_vector (2-1 downto 0);
        y_o : out std_logic_vector (4-1 downto 0)
    );
end entity one_of_four;

Then the instance (sub-block) of such an entity could be used in top.vhd file as follows

-- Sub-block of one_of_four entity
ONE_OF_FOUR : entity work.one_of_four
    port map(
        a_i => s_hex(3 downto 2),
        y_o => disp_dig_o
    );

where work library is the default library in which the compiled entity and architecture units are stored.

The entity definition could also contain a generic. The instance (sub-block) example of such an entity is as follows

--------------------------------------------------------------------
-- Sub-block of binary_cnt entity
BIN_CNT_0 : entity work.binary_cnt
    generic map(
        g_NBIT => 4
    )
    port map(
        clk    => CLK100MHZ,
        reset  => BTN0,   -- Synchronous reset
        en_i   => s_en,   -- Enable
        cnt_o  => s_hex   -- Output bits
    );