pnr
Here are 26 public repositories matching this topic...
Global Travel Assessment System | A passenger data screening and analysis system for enhancing global security
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Dec 27, 2023 - Java
This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been implemented by using Verilog description language which has been synthesized using Design Compiler and Back End design using Synopsys IC Compiler II
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Apr 29, 2024 - Verilog
This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.
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Feb 11, 2024 - Tcl
This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between computer and peripherals. UART mainly contains Transmitter, Receiver and Baud Rate Generator. Baud Rate Generator generates the clock for the UART. We can achieve the desired Baud Rate by using divide factor from sys…
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Mar 30, 2022 - Verilog
Electronic design automation for Minecraft
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May 3, 2019 - Python
This project caters to the extraction of the status of PNR number (Passenger Name Record) of Indian Railways. PNR number is unique to each and every ticket bought in the railways. With the help of it, we can get the exact details of the ticket in hand
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Dec 9, 2021 - Java
Shopping Cart Example
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Apr 23, 2018 - JavaScript
This repository contains my BSc graduation project at the Faculty of Engineering, Ain Shams University. The project focuses on implementing the RISC-V core, specifically the CV32E40 ,with a focus on achieving high performance and maximizing frequency through synthesis, place and route (PNR).
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May 12, 2024 - SystemVerilog
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Nov 15, 2024 - Verilog
This project caters to the extraction of the status of PNR number (Passenger Name Record) of Indian Railways. PNR number is unique to each and every ticket bought in the railways. With the help of it, we can get the exact details of the ticket in hand
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Jun 19, 2019 - Java
RTL to GDSII flow of a low Power configurable multi clock digital system
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Mar 3, 2024 - Verilog
My Graduation Project for BSc of Engineering Ain Shams Uni which is ASIC implementation of PULPino SoC based on the cv32e40p (RISCY) core sponserd by ICpedia using Synopsys tools
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Apr 25, 2024 - Verilog
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Dec 9, 2022 - JavaScript
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Jul 22, 2020 - Shell
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