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fixup! Remove unnecessary freezes pointed out by nikic.
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@topperc
topperc committed Mar 6, 2024
1 parent 354d1fd commit 3b50859
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Showing 3 changed files with 76 additions and 81 deletions.
9 changes: 4 additions & 5 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -7274,7 +7274,6 @@ static SDValue combineSelectToBinOp(SDNode *N, SelectionDAG &DAG,
const APInt &FalseVal = FalseV->getAsAPIntVal();
if (~TrueVal == FalseVal) {
SDValue Neg = DAG.getNegative(CondV, DL, VT);
FalseV = DAG.getFreeze(FalseV);
return DAG.getNode(ISD::XOR, DL, VT, Neg, FalseV);
}
}
Expand All @@ -7290,14 +7289,14 @@ static SDValue combineSelectToBinOp(SDNode *N, SelectionDAG &DAG,
// (select x, x, y) -> x | y
// (select !x, x, y) -> x & y
if (std::optional<bool> MatchResult = matchSetCC(LHS, RHS, CC, TrueV)) {
return DAG.getNode(*MatchResult ? ISD::OR : ISD::AND, DL, VT,
DAG.getFreeze(TrueV), DAG.getFreeze(FalseV));
return DAG.getNode(*MatchResult ? ISD::OR : ISD::AND, DL, VT, TrueV,
FalseV);
}
// (select x, y, x) -> x & y
// (select !x, y, x) -> x | y
if (std::optional<bool> MatchResult = matchSetCC(LHS, RHS, CC, FalseV)) {
return DAG.getNode(*MatchResult ? ISD::AND : ISD::OR, DL, VT,
DAG.getFreeze(TrueV), DAG.getFreeze(FalseV));
return DAG.getNode(*MatchResult ? ISD::AND : ISD::OR, DL, VT, TrueV,
FalseV);
}
}

Expand Down
60 changes: 28 additions & 32 deletions llvm/test/CodeGen/RISCV/fpclamptosat.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1324,8 +1324,8 @@ define i64 @ustest_f64i64(double %x) {
; RV32IF-NEXT: # %bb.4: # %entry
; RV32IF-NEXT: li a0, 1
; RV32IF-NEXT: .LBB20_5: # %entry
; RV32IF-NEXT: lw a4, 8(sp)
; RV32IF-NEXT: lw a3, 12(sp)
; RV32IF-NEXT: lw a3, 8(sp)
; RV32IF-NEXT: lw a4, 12(sp)
; RV32IF-NEXT: and a5, a2, a1
; RV32IF-NEXT: beqz a5, .LBB20_7
; RV32IF-NEXT: # %bb.6: # %entry
Expand All @@ -1334,18 +1334,17 @@ define i64 @ustest_f64i64(double %x) {
; RV32IF-NEXT: .LBB20_7:
; RV32IF-NEXT: snez a1, a0
; RV32IF-NEXT: .LBB20_8: # %entry
; RV32IF-NEXT: and a3, a2, a3
; RV32IF-NEXT: and a4, a2, a4
; RV32IF-NEXT: or a0, a0, a5
; RV32IF-NEXT: and a2, a2, a4
; RV32IF-NEXT: and a2, a2, a3
; RV32IF-NEXT: bnez a0, .LBB20_10
; RV32IF-NEXT: # %bb.9:
; RV32IF-NEXT: snez a0, a3
; RV32IF-NEXT: snez a1, a2
; RV32IF-NEXT: or a1, a1, a0
; RV32IF-NEXT: or a0, a2, a4
; RV32IF-NEXT: snez a1, a0
; RV32IF-NEXT: .LBB20_10: # %entry
; RV32IF-NEXT: neg a1, a1
; RV32IF-NEXT: and a0, a1, a2
; RV32IF-NEXT: and a1, a1, a3
; RV32IF-NEXT: and a1, a1, a4
; RV32IF-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 32
; RV32IF-NEXT: ret
Expand Down Expand Up @@ -1404,8 +1403,8 @@ define i64 @ustest_f64i64(double %x) {
; RV32IFD-NEXT: # %bb.4: # %entry
; RV32IFD-NEXT: li a0, 1
; RV32IFD-NEXT: .LBB20_5: # %entry
; RV32IFD-NEXT: lw a4, 8(sp)
; RV32IFD-NEXT: lw a3, 12(sp)
; RV32IFD-NEXT: lw a3, 8(sp)
; RV32IFD-NEXT: lw a4, 12(sp)
; RV32IFD-NEXT: and a5, a2, a1
; RV32IFD-NEXT: beqz a5, .LBB20_7
; RV32IFD-NEXT: # %bb.6: # %entry
Expand All @@ -1414,18 +1413,17 @@ define i64 @ustest_f64i64(double %x) {
; RV32IFD-NEXT: .LBB20_7:
; RV32IFD-NEXT: snez a1, a0
; RV32IFD-NEXT: .LBB20_8: # %entry
; RV32IFD-NEXT: and a3, a2, a3
; RV32IFD-NEXT: and a4, a2, a4
; RV32IFD-NEXT: or a0, a0, a5
; RV32IFD-NEXT: and a2, a2, a4
; RV32IFD-NEXT: and a2, a2, a3
; RV32IFD-NEXT: bnez a0, .LBB20_10
; RV32IFD-NEXT: # %bb.9:
; RV32IFD-NEXT: snez a0, a3
; RV32IFD-NEXT: snez a1, a2
; RV32IFD-NEXT: or a1, a1, a0
; RV32IFD-NEXT: or a0, a2, a4
; RV32IFD-NEXT: snez a1, a0
; RV32IFD-NEXT: .LBB20_10: # %entry
; RV32IFD-NEXT: neg a1, a1
; RV32IFD-NEXT: and a0, a1, a2
; RV32IFD-NEXT: and a1, a1, a3
; RV32IFD-NEXT: and a1, a1, a4
; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 32
; RV32IFD-NEXT: ret
Expand Down Expand Up @@ -1596,8 +1594,8 @@ define i64 @ustest_f32i64(float %x) {
; RV32-NEXT: # %bb.4: # %entry
; RV32-NEXT: li a0, 1
; RV32-NEXT: .LBB23_5: # %entry
; RV32-NEXT: lw a4, 8(sp)
; RV32-NEXT: lw a3, 12(sp)
; RV32-NEXT: lw a3, 8(sp)
; RV32-NEXT: lw a4, 12(sp)
; RV32-NEXT: and a5, a2, a1
; RV32-NEXT: beqz a5, .LBB23_7
; RV32-NEXT: # %bb.6: # %entry
Expand All @@ -1606,18 +1604,17 @@ define i64 @ustest_f32i64(float %x) {
; RV32-NEXT: .LBB23_7:
; RV32-NEXT: snez a1, a0
; RV32-NEXT: .LBB23_8: # %entry
; RV32-NEXT: and a3, a2, a3
; RV32-NEXT: and a4, a2, a4
; RV32-NEXT: or a0, a0, a5
; RV32-NEXT: and a2, a2, a4
; RV32-NEXT: and a2, a2, a3
; RV32-NEXT: bnez a0, .LBB23_10
; RV32-NEXT: # %bb.9:
; RV32-NEXT: snez a0, a3
; RV32-NEXT: snez a1, a2
; RV32-NEXT: or a1, a1, a0
; RV32-NEXT: or a0, a2, a4
; RV32-NEXT: snez a1, a0
; RV32-NEXT: .LBB23_10: # %entry
; RV32-NEXT: neg a1, a1
; RV32-NEXT: and a0, a1, a2
; RV32-NEXT: and a1, a1, a3
; RV32-NEXT: and a1, a1, a4
; RV32-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 32
; RV32-NEXT: ret
Expand Down Expand Up @@ -1850,8 +1847,8 @@ define i64 @ustest_f16i64(half %x) {
; RV32-NEXT: # %bb.4: # %entry
; RV32-NEXT: li a0, 1
; RV32-NEXT: .LBB26_5: # %entry
; RV32-NEXT: lw a4, 8(sp)
; RV32-NEXT: lw a3, 12(sp)
; RV32-NEXT: lw a3, 8(sp)
; RV32-NEXT: lw a4, 12(sp)
; RV32-NEXT: and a5, a2, a1
; RV32-NEXT: beqz a5, .LBB26_7
; RV32-NEXT: # %bb.6: # %entry
Expand All @@ -1860,18 +1857,17 @@ define i64 @ustest_f16i64(half %x) {
; RV32-NEXT: .LBB26_7:
; RV32-NEXT: snez a1, a0
; RV32-NEXT: .LBB26_8: # %entry
; RV32-NEXT: and a3, a2, a3
; RV32-NEXT: and a4, a2, a4
; RV32-NEXT: or a0, a0, a5
; RV32-NEXT: and a2, a2, a4
; RV32-NEXT: and a2, a2, a3
; RV32-NEXT: bnez a0, .LBB26_10
; RV32-NEXT: # %bb.9:
; RV32-NEXT: snez a0, a3
; RV32-NEXT: snez a1, a2
; RV32-NEXT: or a1, a1, a0
; RV32-NEXT: or a0, a2, a4
; RV32-NEXT: snez a1, a0
; RV32-NEXT: .LBB26_10: # %entry
; RV32-NEXT: neg a1, a1
; RV32-NEXT: and a0, a1, a2
; RV32-NEXT: and a1, a1, a3
; RV32-NEXT: and a1, a1, a4
; RV32-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 32
; RV32-NEXT: ret
Expand Down
88 changes: 44 additions & 44 deletions llvm/test/CodeGen/RISCV/iabs.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -302,56 +302,56 @@ define i128 @abs128(i128 %x) {
; RV32I-LABEL: abs128:
; RV32I: # %bb.0:
; RV32I-NEXT: lw a2, 12(a1)
; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: lw a4, 4(a1)
; RV32I-NEXT: lw a3, 4(a1)
; RV32I-NEXT: lw a4, 0(a1)
; RV32I-NEXT: lw a1, 8(a1)
; RV32I-NEXT: bgez a2, .LBB8_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: neg a5, a1
; RV32I-NEXT: snez a6, a4
; RV32I-NEXT: snez a7, a3
; RV32I-NEXT: or a6, a7, a6
; RV32I-NEXT: sltu t0, a5, a6
; RV32I-NEXT: or a6, a4, a3
; RV32I-NEXT: snez a6, a6
; RV32I-NEXT: sltu a7, a5, a6
; RV32I-NEXT: snez a1, a1
; RV32I-NEXT: add a1, a2, a1
; RV32I-NEXT: neg a1, a1
; RV32I-NEXT: sub a2, a1, t0
; RV32I-NEXT: sub a2, a1, a7
; RV32I-NEXT: sub a1, a5, a6
; RV32I-NEXT: neg a4, a4
; RV32I-NEXT: sub a4, a4, a7
; RV32I-NEXT: snez a5, a4
; RV32I-NEXT: neg a3, a3
; RV32I-NEXT: sub a3, a3, a5
; RV32I-NEXT: neg a4, a4
; RV32I-NEXT: .LBB8_2:
; RV32I-NEXT: sw a3, 0(a0)
; RV32I-NEXT: sw a4, 4(a0)
; RV32I-NEXT: sw a4, 0(a0)
; RV32I-NEXT: sw a1, 8(a0)
; RV32I-NEXT: sw a3, 4(a0)
; RV32I-NEXT: sw a2, 12(a0)
; RV32I-NEXT: ret
;
; RV32ZBB-LABEL: abs128:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: lw a2, 12(a1)
; RV32ZBB-NEXT: lw a3, 0(a1)
; RV32ZBB-NEXT: lw a4, 4(a1)
; RV32ZBB-NEXT: lw a3, 4(a1)
; RV32ZBB-NEXT: lw a4, 0(a1)
; RV32ZBB-NEXT: lw a1, 8(a1)
; RV32ZBB-NEXT: bgez a2, .LBB8_2
; RV32ZBB-NEXT: # %bb.1:
; RV32ZBB-NEXT: neg a5, a1
; RV32ZBB-NEXT: snez a6, a4
; RV32ZBB-NEXT: snez a7, a3
; RV32ZBB-NEXT: or a6, a7, a6
; RV32ZBB-NEXT: sltu t0, a5, a6
; RV32ZBB-NEXT: or a6, a4, a3
; RV32ZBB-NEXT: snez a6, a6
; RV32ZBB-NEXT: sltu a7, a5, a6
; RV32ZBB-NEXT: snez a1, a1
; RV32ZBB-NEXT: add a1, a2, a1
; RV32ZBB-NEXT: neg a1, a1
; RV32ZBB-NEXT: sub a2, a1, t0
; RV32ZBB-NEXT: sub a2, a1, a7
; RV32ZBB-NEXT: sub a1, a5, a6
; RV32ZBB-NEXT: neg a4, a4
; RV32ZBB-NEXT: sub a4, a4, a7
; RV32ZBB-NEXT: snez a5, a4
; RV32ZBB-NEXT: neg a3, a3
; RV32ZBB-NEXT: sub a3, a3, a5
; RV32ZBB-NEXT: neg a4, a4
; RV32ZBB-NEXT: .LBB8_2:
; RV32ZBB-NEXT: sw a3, 0(a0)
; RV32ZBB-NEXT: sw a4, 4(a0)
; RV32ZBB-NEXT: sw a4, 0(a0)
; RV32ZBB-NEXT: sw a1, 8(a0)
; RV32ZBB-NEXT: sw a3, 4(a0)
; RV32ZBB-NEXT: sw a2, 12(a0)
; RV32ZBB-NEXT: ret
;
Expand Down Expand Up @@ -384,56 +384,56 @@ define i128 @select_abs128(i128 %x) {
; RV32I-LABEL: select_abs128:
; RV32I: # %bb.0:
; RV32I-NEXT: lw a2, 12(a1)
; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: lw a4, 4(a1)
; RV32I-NEXT: lw a3, 4(a1)
; RV32I-NEXT: lw a4, 0(a1)
; RV32I-NEXT: lw a1, 8(a1)
; RV32I-NEXT: bgez a2, .LBB9_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: neg a5, a1
; RV32I-NEXT: snez a6, a4
; RV32I-NEXT: snez a7, a3
; RV32I-NEXT: or a6, a7, a6
; RV32I-NEXT: sltu t0, a5, a6
; RV32I-NEXT: or a6, a4, a3
; RV32I-NEXT: snez a6, a6
; RV32I-NEXT: sltu a7, a5, a6
; RV32I-NEXT: snez a1, a1
; RV32I-NEXT: add a1, a2, a1
; RV32I-NEXT: neg a1, a1
; RV32I-NEXT: sub a2, a1, t0
; RV32I-NEXT: sub a2, a1, a7
; RV32I-NEXT: sub a1, a5, a6
; RV32I-NEXT: neg a4, a4
; RV32I-NEXT: sub a4, a4, a7
; RV32I-NEXT: snez a5, a4
; RV32I-NEXT: neg a3, a3
; RV32I-NEXT: sub a3, a3, a5
; RV32I-NEXT: neg a4, a4
; RV32I-NEXT: .LBB9_2:
; RV32I-NEXT: sw a3, 0(a0)
; RV32I-NEXT: sw a4, 4(a0)
; RV32I-NEXT: sw a4, 0(a0)
; RV32I-NEXT: sw a1, 8(a0)
; RV32I-NEXT: sw a3, 4(a0)
; RV32I-NEXT: sw a2, 12(a0)
; RV32I-NEXT: ret
;
; RV32ZBB-LABEL: select_abs128:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: lw a2, 12(a1)
; RV32ZBB-NEXT: lw a3, 0(a1)
; RV32ZBB-NEXT: lw a4, 4(a1)
; RV32ZBB-NEXT: lw a3, 4(a1)
; RV32ZBB-NEXT: lw a4, 0(a1)
; RV32ZBB-NEXT: lw a1, 8(a1)
; RV32ZBB-NEXT: bgez a2, .LBB9_2
; RV32ZBB-NEXT: # %bb.1:
; RV32ZBB-NEXT: neg a5, a1
; RV32ZBB-NEXT: snez a6, a4
; RV32ZBB-NEXT: snez a7, a3
; RV32ZBB-NEXT: or a6, a7, a6
; RV32ZBB-NEXT: sltu t0, a5, a6
; RV32ZBB-NEXT: or a6, a4, a3
; RV32ZBB-NEXT: snez a6, a6
; RV32ZBB-NEXT: sltu a7, a5, a6
; RV32ZBB-NEXT: snez a1, a1
; RV32ZBB-NEXT: add a1, a2, a1
; RV32ZBB-NEXT: neg a1, a1
; RV32ZBB-NEXT: sub a2, a1, t0
; RV32ZBB-NEXT: sub a2, a1, a7
; RV32ZBB-NEXT: sub a1, a5, a6
; RV32ZBB-NEXT: neg a4, a4
; RV32ZBB-NEXT: sub a4, a4, a7
; RV32ZBB-NEXT: snez a5, a4
; RV32ZBB-NEXT: neg a3, a3
; RV32ZBB-NEXT: sub a3, a3, a5
; RV32ZBB-NEXT: neg a4, a4
; RV32ZBB-NEXT: .LBB9_2:
; RV32ZBB-NEXT: sw a3, 0(a0)
; RV32ZBB-NEXT: sw a4, 4(a0)
; RV32ZBB-NEXT: sw a4, 0(a0)
; RV32ZBB-NEXT: sw a1, 8(a0)
; RV32ZBB-NEXT: sw a3, 4(a0)
; RV32ZBB-NEXT: sw a2, 12(a0)
; RV32ZBB-NEXT: ret
;
Expand Down

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