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Fix zext
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Consider large constant.
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@tyfkda
tyfkda committed May 9, 2024
1 parent 3679295 commit 5052e77
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Showing 3 changed files with 49 additions and 25 deletions.
47 changes: 36 additions & 11 deletions src/as/arch/riscv64/asm_code.c
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Original file line number Diff line number Diff line change
Expand Up @@ -134,17 +134,42 @@ static unsigned char *asm_2ri(Inst *inst, Code *code) {
}
}
switch (inst->op) {
case ADDI: W_ADDI(rd, rs, imm); break;
case ADDIW: W_ADDIW(rd, rs, imm); break;
case ANDI: W_ANDI(rd, rs, imm); break;
case ORI: W_ORI(rd, rs, imm); break;
case XORI: W_XORI(rd, rs, imm); break;
case SLLI: W_SLLI(rd, rs, imm); break;
case SLLIW: W_SLLIW(rd, rs, imm); break;
case SRLI: W_SRLI(rd, rs, imm); break;
case SRAI: W_SRAI(rd, rs, imm); break;
case SLTI: W_SLTI(rd, rs, imm); break;
case SLTIU: W_SLTIU(rd, rs, imm); break;
case ADDI:
case ADDIW:
case ANDI:
case ORI:
case XORI:
if (imm >= 2048 || imm < -2048)
return NULL;
switch (inst->op) {
case ADDI: W_ADDI(rd, rs, imm); break;
case ADDIW: W_ADDIW(rd, rs, imm); break;
case ANDI: W_ANDI(rd, rs, imm); break;
case ORI: W_ORI(rd, rs, imm); break;
case XORI: W_XORI(rd, rs, imm); break;
default: assert(false); break;
}
break;

case SLLI:
case SLLIW:
case SRLI:
case SRAI:
case SLTI:
case SLTIU:
if (imm >= 64 || (inst->op == SLLIW && imm >= 32) || imm < 0)
return NULL;
switch (inst->op) {
case SLLI: W_SLLI(rd, rs, imm); break;
case SLLIW: W_SLLIW(rd, rs, imm); break;
case SRLI: W_SRLI(rd, rs, imm); break;
case SRAI: W_SRAI(rd, rs, imm); break;
case SLTI: W_SLTI(rd, rs, imm); break;
case SLTIU: W_SLTIU(rd, rs, imm); break;
default: assert(false); break;
}
break;

default: assert(false); return NULL;
}
return code->buf;
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8 changes: 4 additions & 4 deletions src/as/arch/riscv64/riscv64_code.h
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Original file line number Diff line number Diff line change
Expand Up @@ -160,12 +160,12 @@
#define P_LI(rd, imm) W_ADDI(rd, ZERO, imm)
#define P_NEG(rd, rs) W_SUB(rd, ZERO, rs)
#define P_NOT(rd, rs) W_XORI(rd, rs, -1)
#define P_SEXT_B(rd, rs) do { if ((rd) == (rs) && (rs) != 0) C_SLLI(rd, 56); else W_SLLI(rd, rs, 56); C_SRAI(rd, 56); } while (0)
#define P_SEXT_H(rd, rs) do { if ((rd) == (rs) && (rs) != 0) C_SLLI(rd, 48); else W_SLLI(rd, rs, 48); C_SRAI(rd, 48); } while (0)
#define P_SEXT_B(rd, rs) do { if ((rd) == (rs)) C_SLLI(rd, 56); else W_SLLI(rd, rs, 56); if (is_rvc_reg(rd)) C_SRAI(rd, 56); else W_SRAI(rd, rd, 56); } while (0)
#define P_SEXT_H(rd, rs) do { if ((rd) == (rs)) C_SLLI(rd, 48); else W_SLLI(rd, rs, 48); if (is_rvc_reg(rd)) C_SRAI(rd, 48); else W_SRAI(rd, rd, 48); } while (0)
#define P_SEXT_W(rd, rs) do { if ((rd) == (rs)) C_ADDIW(rd, 0); else W_ADDIW(rd, rs, 0); } while (0)
#define P_ZEXT_B(rd, rs) W_ANDI(rd, rs, 0xff)
#define P_ZEXT_H(rd, rs) do { if ((rd) == (rs) && (rs) != 0) C_SLLI(rd, 48); else W_SLLI(rd, rs, 48); C_SRLI(rd, 48); } while (0)
#define P_ZEXT_W(rd, rs) do { if ((rd) == (rs) && (rs) != 0) C_SLLI(rd, 32); else W_SLLI(rd, rs, 32); C_SRLI(rd, 32); } while (0)
#define P_ZEXT_H(rd, rs) do { if ((rd) == (rs)) C_SLLI(rd, 48); else W_SLLI(rd, rs, 48); if (is_rvc_reg(rd)) C_SRLI(rd, 48); else W_SRLI(rd, rd, 48); } while (0)
#define P_ZEXT_W(rd, rs) do { if ((rd) == (rs)) C_SLLI(rd, 32); else W_SLLI(rd, rs, 32); if (is_rvc_reg(rd)) C_SRLI(rd, 32); else W_SRLI(rd, rd, 32); } while (0)
#define P_SEQZ(rd, rs) W_SLTIU(rd, rs, 1)
#define P_SNEZ(rd, rs) W_SLTU(rd, ZERO, rs)
#define P_SLTZ(rd, rs) W_SLT(rd, rs, ZERO)
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19 changes: 9 additions & 10 deletions src/cc/arch/riscv64/ir_riscv64.c
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Original file line number Diff line number Diff line change
Expand Up @@ -987,8 +987,6 @@ static void insert_const_mov(VReg **pvreg, RegAlloc *ra, Vector *irs, int i) {
#define insert_tmp_mov insert_const_mov

void tweak_irs(FuncBackend *fnbe) {
UNUSED(fnbe);

BBContainer *bbcon = fnbe->bbcon;
RegAlloc *ra = fnbe->ra;
for (int i = 0; i < bbcon->bbs->len; ++i) {
Expand All @@ -1011,10 +1009,9 @@ void tweak_irs(FuncBackend *fnbe) {
assert(!(ir->opr1->flag & VRF_CONST) || !(ir->opr2->flag & VRF_CONST));
if (ir->opr1->flag & VRF_CONST)
swap_opr12(ir);
if (ir->opr2->flag & VRF_CONST) {
if (ir->opr2->fixnum > 0x0fff || ir->opr2->fixnum < -0x0fff)
insert_const_mov(&ir->opr2, ra, irs, j++);
}
if ((ir->opr2->flag & VRF_CONST) &&
(ir->opr2->fixnum > 0x07ff || ir->opr2->fixnum < -0x0800))
insert_const_mov(&ir->opr2, ra, irs, j++);
break;
case IR_SUB:
assert(!(ir->opr1->flag & VRF_CONST) || !(ir->opr2->flag & VRF_CONST));
Expand All @@ -1027,10 +1024,9 @@ void tweak_irs(FuncBackend *fnbe) {
}
insert_const_mov(&ir->opr1, ra, irs, j++);
}
if (ir->opr2->flag & VRF_CONST) {
if (ir->opr2->fixnum > 0x0fff || ir->opr2->fixnum < -0x0fff)
insert_const_mov(&ir->opr2, ra, irs, j++);
}
if ((ir->opr2->flag & VRF_CONST) &&
(ir->opr2->fixnum > 0x0800 || ir->opr2->fixnum < -0x07ff))
insert_const_mov(&ir->opr2, ra, irs, j++);
break;
case IR_MUL:
case IR_DIV:
Expand Down Expand Up @@ -1070,6 +1066,9 @@ void tweak_irs(FuncBackend *fnbe) {
if (dst->vsize != ir->opr1->vsize)
dst = reg_alloc_spawn(ra, ir->opr1->vsize, ir->opr1->flag & VRF_MASK);

if ((ir->opr2->flag & VRF_CONST) &&
(ir->opr2->fixnum > 0x0800 || ir->opr2->fixnum < -0x07ff))
insert_const_mov(&ir->opr2, ra, irs, j++);
IR *sub = new_ir_bop_raw(IR_SUB, dst, ir->opr1, ir->opr2, ir->flag);
vec_insert(irs, j++, sub);

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