suntestedInnovus implementationn, runs properly thru unit tests & moc…

…k_hier e2e test

e2e/configs-design/pass/mock_hier.yml

@@ -9,11 +9,12 @@ synthesis.inputs:
   input_files: ["src/pass.v"]
 
 vlsi.inputs.hierarchical:
-  mode: hierarchical
-  top_module: ChipTop
+  #mode: hierarchical
+  mode: top-down
+  top_module: pass
   config_source: manual
   manual_modules:
-    - ChipTop:
+    - pass:
         - SubModA
         - SubModB
     - SubModA:
@@ -22,7 +23,7 @@ vlsi.inputs.hierarchical:
     - SubModB:
         - SubModE
   manual_placement_constraints:
-    - ChipTop: []
+    - pass: []
     - SubModA: []
     - SubModB: []
     - SubModC: []

hammer/config/defaults.yml

@@ -133,7 +133,11 @@ vlsi.inputs:
     # hierarchical - Same as bottom-up (legacy).
 
     module_mode: flat # Hierarchical par mode for the current module. (str)
-    # This is not user-set. It is dynamically set as you traverse through the hierarchical dependency graph.
+    # Generally not user-set. It is dynamically set as you traverse through the hierarchical dependency graph.
+
+    partitioning: true # Whether the current module in the top-down flow is undergoing partitioning. (bool)
+    # If false, it will be undergoing assembly.
+    # Generally not user-set. It is dynamically set as you traverse through the hierarchical dependency graph.
 
     top_module: "null" # Top RTL module in the hierarchical flow. (str)
     # Not to be confused with synthesis.inputs.top_module which specifies the synthesis module for this run.
@@ -481,6 +485,12 @@ par.inputs:
   # Typically a list of Verilog/VHDL files, depending on the tool.
   # For place and route, these should typically be post-synthesis netlists.
 
+  input_dbs: [] # Input databases.
+  # Input databases used in top-down hierarchical flow.
+  # Partitioning should be triggered if the post-partitioning database of the current module is not found in this list.
+  # Otherwise, assembly should be triggered.
+  # Generally set by linking steps, but can be manually overridden.
+
   top_module: null # Top RTL module.
 
   post_synth_sdc: null # Optional: SDC input file from post-synthesis.

hammer/config/defaults_types.yml

@@ -94,6 +94,9 @@ vlsi.inputs:
     # Hierarchical par mode of the current module. (str)
     module_mode: str
 
+    # Partitioning status of the current module. (bool)
+    partitioning: bool
+
     # Top RTL module in the hierarchical flow. (str)
     top_module: str
 
@@ -229,6 +232,9 @@ par.inputs:
   # Input post-synthesis netlist files.
   input_files: list[str]
 
+  # Input databases.
+  input_dbs: list[str]
+
   # Top RTL module.
   top_module: Optional[str]
 

hammer/generate_properties.py

@@ -133,6 +133,8 @@ def main(args) -> int:
                                         inputs=[
                                             InterfaceVar("input_files", "List[str]",
                                                          "input post-synthesis netlist files"),
+                                            InterfaceVar("input_dbs", "List[str]",
+                                                         "(optional) input database files/dirs for top-down hierarchical mode"),
                                             InterfaceVar("post_synth_sdc", "Optional[str]",
                                                          "(optional) input post-synthesis SDC constraint file"),
                                         ],
@@ -141,7 +143,9 @@ def main(args) -> int:
 
                                             # e.g. par-rundir/TopModuleILMDir/mmmc/ilm_data/TopModule. Has a bunch of files TopModule_postRoute*
                                             InterfaceVar("output_ilms", "List[ILMStruct]",
-                                                         "(optional) output ILM information for hierarchical mode"),
+                                                         "(optional) output ILM information for bottom-up hierarchical mode"),
+                                            InterfaceVar("output_dbs", "List[str]",
+                                                         "(optional) output database files/dirs for each partition in top-down hierarchical mode"),
                                             InterfaceVar("output_gds", "str", "path to the output GDS file"),
                                             InterfaceVar("output_netlist", "str", "path to the output netlist file"),
                                             InterfaceVar("output_sim_netlist", "str", "path to the output simulation netlist file"),

hammer/lvs/mocklvs/__init__.py

@@ -29,7 +29,7 @@ def lvs_results(self) -> List[str]:
         return ["VDD is connected to VSS"]
 
     def get_ilms(self) -> bool:
-        if self.hierarchical_mode in [HierarchicalMode.Hierarchical, HierarchicalMode.Top]:
+        if self.hierarchical_mode.is_nonleaf_hierarchical():
             with open(os.path.join(self.run_dir, "input_ilms.json"), "w") as f:
                 f.write(json.dumps(list(map(lambda s: s.to_setting(), self.get_input_ilms()))))
         return True