Top-down hierarchical

e2e/configs-design/pass/mock_hier.yml

@@ -9,11 +9,12 @@ synthesis.inputs:
   input_files: ["src/pass.v"]
 
 vlsi.inputs.hierarchical:
-  mode: hierarchical
-  top_module: ChipTop
+  #mode: hierarchical
+  mode: top-down
+  top_module: pass
   config_source: manual
   manual_modules:
-    - ChipTop:
+    - pass:
         - SubModA
         - SubModB
     - SubModA:
@@ -22,7 +23,7 @@ vlsi.inputs.hierarchical:
     - SubModB:
         - SubModE
   manual_placement_constraints:
-    - ChipTop: []
+    - pass: []
     - SubModA: []
     - SubModB: []
     - SubModC: []

hammer/config/defaults.yml

@@ -60,13 +60,13 @@ vlsi.technology:
   bump_block_cut_layer: null # Top cut/via layer for blockage under bumps. (Optional[str])
   # Only used if using vlsi.inputs.bumps
   # TODO: remove this after stackup supports vias ucb-bar/hammer#354
-  
+
   tap_cell_interval: 10.0 # Spacing between columns of tap cells (float)
   # Must be overridden by technology plugin defaults or else you will have DRC/latch-up errors.
 
   tap_cell_offset: 0.0 # Offset of the first column of tape cells from the edge of the floorplan (float)
   # Should be overridden by technology plugin defaults.
-  
+
   routing_layers: null # If specified, set/override the [bottom, top] layers used for routing. (Optional[Tuple[int, int]])
   # Both must match the index number (not name) of layers used in the stackup.
 
@@ -103,7 +103,7 @@ vlsi.technology:
 
   timing_lib_pref: "NLDM"
   # Select a timing lib preference, available options include:
-  # NLDM, ECSM, and CCS (lower or upper case acceptable). 
+  # NLDM, ECSM, and CCS (lower or upper case acceptable).
   # If no preference is specified, then the following preference order is followed:
   # NLDM -> ECSM -> CCS
 
@@ -124,12 +124,20 @@ vlsi.inputs:
     GND: "0 V" # GND (str): The default voltage of the primary ground net
 
   hierarchical:
-    mode: flat # Hierarchical par mode. (str)
+    mode: flat # User-defined hierarchical flow mode. (str)
+    # This determines how the build system will handle hierarchical designs.
     # Valid options:
-    # flat - Perform a flat place and route run.
-    # leaf - Leaf module in a hierarchical run - same as flat except that an extra write_ilm step is added.
-    # hierarchical - Module which has sub-modules which are also hierarchical.
-    # top - Top module in a hierarchical run - runs an extra assemble_design step.
+    # flat - Perform a flat flow.
+    # top_down - Perform a top-down hierarchical flow.
+    # bottom_up - Perform a bottom-up hierarchical flow.
+    # hierarchical - Same as bottom-up (legacy).
+
+    module_mode: flat # Hierarchical par mode for the current module. (str)
+    # Generally not user-set. It is dynamically set as you traverse through the hierarchical dependency graph.
+
+    partitioning: true # Whether the current module in the top-down flow is undergoing partitioning. (bool)
+    # If false, it will be undergoing assembly.
+    # Generally not user-set. It is dynamically set as you traverse through the hierarchical dependency graph.
 
     top_module: "null" # Top RTL module in the hierarchical flow. (str)
     # Not to be confused with synthesis.inputs.top_module which specifies the synthesis module for this run.
@@ -323,7 +331,7 @@ vlsi.inputs:
     # type: float
     pitch: 0.0
     global_x_offset: 0.0 # offset the bump map in the x-axis (float)
-    global_y_offset: 0.0 # offset the bump map in the y-axis (float)    
+    global_y_offset: 0.0 # offset the bump map in the y-axis (float)
     cell: "" # cell (str) - Name of the default bump cell
     assignments: [] # assignments - List of BumpAssignment structs. You must specify one of name or no_connect.
     # If both are specified the bump will be left unconnected
@@ -477,6 +485,12 @@ par.inputs:
   # Typically a list of Verilog/VHDL files, depending on the tool.
   # For place and route, these should typically be post-synthesis netlists.
 
+  input_dbs: [] # Input databases.
+  # Input databases used in top-down hierarchical flow.
+  # Partitioning should be triggered if the post-partitioning database of the current module is not found in this list.
+  # Otherwise, assembly should be triggered.
+  # Generally set by linking steps, but can be manually overridden.
+
   top_module: null # Top RTL module.
 
   post_synth_sdc: null # Optional: SDC input file from post-synthesis.
@@ -879,7 +893,7 @@ power.inputs:
   #       "write_profile" - profiles all power types on all categories for all the sub-hierarchies for a given design instance (*.fsdb)
   #       "profile" - run plot_profile + dump_profile
   #       "all" - generate all of the above report formats
-  
+
   # examples:
   #   report_configs: [{waveform_path: "/path/to/fsdb", module: "chiptop", levels:3, start_time: "0ns", end_time: "1ns", toggle_signal:"/ChipTop/clock", num_toggles:1, frame_count:1000, report_name: "my_fsdb_report"}]
   #   report_configs: [{waveform_path: "/path/to/fsdb", inst: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile", interval_size: "1ns", output_formats: ["plot_profile"]}]

hammer/config/defaults_types.yml

@@ -58,7 +58,7 @@ vlsi.technology:
 
   # Offset of the first column of tape cells from the edge of the floorplan
   # type: float
-  tap_cell_offset: float 
+  tap_cell_offset: float
 
   # Set the [bottom, top] layer used for routing. (Optional[Tuple[int, int]])
   routing_layers: Optional[list[int]]
@@ -88,9 +88,15 @@ vlsi.inputs:
     GND: str
 
   hierarchical:
-    # Hierarchical par mode. (str)
+    # Flow mode. (str)
     mode: str
 
+    # Hierarchical par mode of the current module. (str)
+    module_mode: str
+
+    # Partitioning status of the current module. (bool)
+    partitioning: bool
+
     # Top RTL module in the hierarchical flow. (str)
     top_module: str
 
@@ -157,9 +163,9 @@ vlsi.inputs:
     y: int
     # pitch (float) - pitch of bumps in microns
     pitch: float
-    # global_x_offset (float) - offset the bump map in the x-axis 
+    # global_x_offset (float) - offset the bump map in the x-axis
     global_x_offset: float
-    # global_y_offset (float) - offset the bump map in the y-axis 
+    # global_y_offset (float) - offset the bump map in the y-axis
     global_y_offset: float
     # cell (str) - Name of the default bump cell
     cell: str
@@ -226,6 +232,9 @@ par.inputs:
   # Input post-synthesis netlist files.
   input_files: list[str]
 
+  # Input databases.
+  input_dbs: list[str]
+
   # Top RTL module.
   top_module: Optional[str]
 

hammer/generate_properties.py

@@ -133,6 +133,8 @@ def main(args) -> int:
                                         inputs=[
                                             InterfaceVar("input_files", "List[str]",
                                                          "input post-synthesis netlist files"),
+                                            InterfaceVar("input_dbs", "List[str]",
+                                                         "(optional) input database files/dirs for top-down hierarchical mode"),
                                             InterfaceVar("post_synth_sdc", "Optional[str]",
                                                          "(optional) input post-synthesis SDC constraint file"),
                                         ],
@@ -141,7 +143,9 @@ def main(args) -> int:
 
                                             # e.g. par-rundir/TopModuleILMDir/mmmc/ilm_data/TopModule. Has a bunch of files TopModule_postRoute*
                                             InterfaceVar("output_ilms", "List[ILMStruct]",
-                                                         "(optional) output ILM information for hierarchical mode"),
+                                                         "(optional) output ILM information for bottom-up hierarchical mode"),
+                                            InterfaceVar("output_dbs", "List[str]",
+                                                         "(optional) output database files/dirs for each partition in top-down hierarchical mode"),
                                             InterfaceVar("output_gds", "str", "path to the output GDS file"),
                                             InterfaceVar("output_netlist", "str", "path to the output netlist file"),
                                             InterfaceVar("output_sim_netlist", "str", "path to the output simulation netlist file"),

hammer/lvs/mocklvs/__init__.py

@@ -29,7 +29,7 @@ def lvs_results(self) -> List[str]:
         return ["VDD is connected to VSS"]
 
     def get_ilms(self) -> bool:
-        if self.hierarchical_mode in [HierarchicalMode.Hierarchical, HierarchicalMode.Top]:
+        if self.hierarchical_mode.is_nonleaf_hierarchical():
             with open(os.path.join(self.run_dir, "input_ilms.json"), "w") as f:
                 f.write(json.dumps(list(map(lambda s: s.to_setting(), self.get_input_ilms()))))
         return True