update golden result

verilog-to-routing · Aug 21, 2024 · 0a0f5c8 · 0a0f5c8
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commit 0a0f5c8
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diff --git a/vtr_flow/parse/pass_requirements/common/pass_requirements.vpr_route_min_chan_width.txt b/vtr_flow/parse/pass_requirements/common/pass_requirements.vpr_route_min_chan_width.txt
@@ -11,7 +11,7 @@ min_chan_width_routing_area_total;Range(0.7,1.3)
 min_chan_width_routing_area_per_tile;Range(0.7,1.3)
 
 #Run-time metrics
-min_chan_width_route_time;RangeAbs(0.10,15.0,2)
+min_chan_width_route_time;RangeAbs(0.10,15.0,3)
 
 #Peak memory
 #We set a 100MiB minimum threshold since the memory