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Fix libs dir confilict with master
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@amin1377
amin1377 committed Aug 16, 2024
1 parent b57dcaa commit 6daebce
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Showing 7 changed files with 65 additions and 21 deletions.
2 changes: 1 addition & 1 deletion libs/librrgraph/src/io/gen/README.gen.md
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Original file line number Diff line number Diff line change
Expand Up @@ -2,4 +2,4 @@
`rr_graph_uxsdcxx_interface.h` are generated via uxsdcxx and are checked in to
avoid requiring python3 and the uxsdcxx depedencies to build VPR.

See `vpr/src/route/gen/SCHEMA_GENERATOR.md` for details.
See `$VTR_DIR/libs/librrgraph/src/base/SCHEMA_GENERATOR.md` for details.
40 changes: 33 additions & 7 deletions libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h
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Expand Up @@ -4,9 +4,9 @@
* https://github.com/duck2/uxsdcxx
* Modify only if your build process doesn't involve regenerating this file.
*
* Cmdline: /home/talaeikh/uxsdcxx/uxsdcxx.py /home/talaeikh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
* Input file: /home/talaeikh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
* md5sum of input file: 9c14a0ddd3c6bc1e690ca6abf467bae6
* Cmdline: uxsdcxx/uxsdcxx.py /home/mohagh18/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
* Input file: /home/mohagh18/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
* md5sum of input file: 65eddcc840064bbb91d7f4cf0b8bf821
*/

#include <functional>
Expand Down Expand Up @@ -247,8 +247,8 @@ constexpr const char *atok_lookup_t_segment_timing[] = {"C_per_meter", "R_per_me

enum class gtok_t_segment {TIMING};
constexpr const char *gtok_lookup_t_segment[] = {"timing"};
enum class atok_t_segment {ID, NAME, RES_TYPE};
constexpr const char *atok_lookup_t_segment[] = {"id", "name", "res_type"};
enum class atok_t_segment {ID, LENGTH, NAME, RES_TYPE};
constexpr const char *atok_lookup_t_segment[] = {"id", "length", "name", "res_type"};

enum class gtok_t_segments {SEGMENT};
constexpr const char *gtok_lookup_t_segments[] = {"segment"};
Expand Down Expand Up @@ -792,6 +792,24 @@ inline atok_t_segment lex_attr_t_segment(const char *in, const std::function<voi
default: break;
}
break;
case 6:
switch(*((triehash_uu32*)&in[0])){
case onechar('l', 0, 32) | onechar('e', 8, 32) | onechar('n', 16, 32) | onechar('g', 24, 32):
switch(in[4]){
case onechar('t', 0, 8):
switch(in[5]){
case onechar('h', 0, 8):
return atok_t_segment::LENGTH;
break;
default: break;
}
break;
default: break;
}
break;
default: break;
}
break;
case 8:
switch(*((triehash_uu64*)&in[0])){
case onechar('r', 0, 64) | onechar('e', 8, 64) | onechar('s', 16, 64) | onechar('_', 24, 64) | onechar('t', 32, 64) | onechar('y', 40, 64) | onechar('p', 48, 64) | onechar('e', 56, 64):
Expand Down Expand Up @@ -2325,7 +2343,7 @@ inline void load_switch_required_attributes(const pugi::xml_node &root, int * id
}

inline void load_segment_required_attributes(const pugi::xml_node &root, int * id, const std::function<void(const char *)> * report_error){
std::bitset<3> astate = 0;
std::bitset<4> astate = 0;
for(pugi::xml_attribute attr = root.first_attribute(); attr; attr = attr.next_attribute()){
atok_t_segment in = lex_attr_t_segment(attr.name(), report_error);
if(astate[(int)in] == 0) astate[(int)in] = 1;
Expand All @@ -2334,6 +2352,9 @@ inline void load_segment_required_attributes(const pugi::xml_node &root, int * i
case atok_t_segment::ID:
*id = load_int(attr.value(), report_error);
break;
case atok_t_segment::LENGTH:
/* Attribute length set after element init */
break;
case atok_t_segment::NAME:
/* Attribute name set after element init */
break;
Expand All @@ -2343,7 +2364,7 @@ inline void load_segment_required_attributes(const pugi::xml_node &root, int * i
default: break; /* Not possible. */
}
}
std::bitset<3> test_astate = astate | std::bitset<3>(0b100);
std::bitset<4> test_astate = astate | std::bitset<4>(0b1010);
if(!test_astate.all()) attr_error(test_astate, atok_lookup_t_segment, report_error);
}

Expand Down Expand Up @@ -2936,6 +2957,9 @@ inline void load_segment(const pugi::xml_node &root, T &out, Context &context, c
case atok_t_segment::ID:
/* Attribute id is already set */
break;
case atok_t_segment::LENGTH:
out.set_segment_length(load_int(attr.value(), report_error), context);
break;
case atok_t_segment::NAME:
out.set_segment_name(attr.value(), context);
break;
Expand Down Expand Up @@ -4006,6 +4030,8 @@ inline void write_segments(T &in, std::ostream &os, Context &context){
auto child_context = in.get_segments_segment(i, context);
os << "<segment";
os << " id=\"" << in.get_segment_id(child_context) << "\"";
if((bool)in.get_segment_length(child_context))
os << " length=\"" << in.get_segment_length(child_context) << "\"";
os << " name=\"" << in.get_segment_name(child_context) << "\"";
if((bool)in.get_segment_res_type(child_context))
os << " res_type=\"" << lookup_segment_res_type[(int)in.get_segment_res_type(child_context)] << "\"";
Expand Down
9 changes: 6 additions & 3 deletions libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_capnp.h
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Original file line number Diff line number Diff line change
Expand Up @@ -4,9 +4,9 @@
* https://github.com/duck2/uxsdcxx
* Modify only if your build process doesn't involve regenerating this file.
*
* Cmdline: /home/talaeikh/uxsdcxx/uxsdcap.py /home/talaeikh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
* Input file: /home/talaeikh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
* md5sum of input file: 9c14a0ddd3c6bc1e690ca6abf467bae6
* Cmdline: uxsdcxx/uxsdcap.py /home/mohagh18/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
* Input file: /home/mohagh18/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
* md5sum of input file: 65eddcc840064bbb91d7f4cf0b8bf821
*/

#include <functional>
Expand Down Expand Up @@ -601,6 +601,7 @@ inline void load_segment_capnp_type(const ucap::Segment::Reader &root, T &out, C
(void)report_error;
(void)stack;

out.set_segment_length(root.getLength(), context);
out.set_segment_name(root.getName().cStr(), context);
out.set_segment_res_type(conv_enum_segment_res_type(root.getResType(), report_error), context);
stack->push_back(std::make_pair("getTiming", 0));
Expand Down Expand Up @@ -1101,6 +1102,8 @@ inline void write_segments_capnp_type(T &in, ucap::Segments::Builder &root, Cont
auto segments_segment = segments_segments[i];
auto child_context = in.get_segments_segment(i, context);
segments_segment.setId(in.get_segment_id(child_context));
if((bool)in.get_segment_length(child_context))
segments_segment.setLength(in.get_segment_length(child_context));
segments_segment.setName(in.get_segment_name(child_context));
if((bool)in.get_segment_res_type(child_context))
segments_segment.setResType(conv_to_enum_segment_res_type(in.get_segment_res_type(child_context)));
Expand Down
9 changes: 6 additions & 3 deletions libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_interface.h
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Original file line number Diff line number Diff line change
Expand Up @@ -4,9 +4,9 @@
* https://github.com/duck2/uxsdcxx
* Modify only if your build process doesn't involve regenerating this file.
*
* Cmdline: /home/talaeikh/uxsdcxx/uxsdcxx.py /home/talaeikh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
* Input file: /home/talaeikh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
* md5sum of input file: 9c14a0ddd3c6bc1e690ca6abf467bae6
* Cmdline: uxsdcxx/uxsdcxx.py /home/mohagh18/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
* Input file: /home/mohagh18/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
* md5sum of input file: 65eddcc840064bbb91d7f4cf0b8bf821
*/

#include <functional>
Expand Down Expand Up @@ -245,11 +245,14 @@ class RrGraphBase {
* <xs:element minOccurs="0" name="timing" type="segment_timing" />
* </xs:all>
* <xs:attribute name="id" type="xs:int" use="required" />
* <xs:attribute name="length" type="xs:int" />
* <xs:attribute name="name" type="xs:string" use="required" />
* <xs:attribute name="res_type" type="segment_res_type" />
* </xs:complexType>
*/
virtual inline int get_segment_id(typename ContextTypes::SegmentReadContext &ctx) = 0;
virtual inline int get_segment_length(typename ContextTypes::SegmentReadContext &ctx) = 0;
virtual inline void set_segment_length(int length, typename ContextTypes::SegmentWriteContext &ctx) = 0;
virtual inline const char * get_segment_name(typename ContextTypes::SegmentReadContext &ctx) = 0;
virtual inline void set_segment_name(const char * name, typename ContextTypes::SegmentWriteContext &ctx) = 0;
virtual inline enum_segment_res_type get_segment_res_type(typename ContextTypes::SegmentReadContext &ctx) = 0;
Expand Down
1 change: 1 addition & 0 deletions libs/librrgraph/src/io/rr_graph.xsd
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Expand Up @@ -155,6 +155,7 @@
<xs:element name="timing" type="segment_timing" minOccurs="0"/>
</xs:all>
<xs:attribute name="id" type="xs:int" use="required"/>
<xs:attribute name="length" type="xs:int"/>
<xs:attribute name="name" type="xs:string" use="required"/>
<xs:attribute name="res_type" type="segment_res_type"/>
</xs:complexType>
Expand Down
10 changes: 10 additions & 0 deletions libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1347,13 +1347,23 @@ class RrGraphSerializer final : public uxsd::RrGraphBase<RrGraphContextTypes> {
inline const char* get_segment_name(const t_segment_inf*& segment) final {
return segment->name.c_str();
}
inline int get_segment_length(const t_segment_inf*& segment) final {
return segment->length;
}
inline void set_segment_name(const char* name, const t_segment_inf*& segment) final {
if (segment->name != name) {
report_error(
"Architecture file does not match RR graph's segment name: arch uses %s, RR graph uses %s",
segment->name.c_str(), name);
}
}
inline void set_segment_length(int length, const t_segment_inf*& segment) final {
if (segment->length != length) {
report_error(
"Architecture file does not match RR graph's length: arch uses %d, RR graph uses %d",
segment->length, length);
}
}
inline uxsd::enum_segment_res_type get_segment_res_type(const t_segment_inf*& segment) final {
return to_uxsd_segment_res_type(segment->res_type);
}
Expand Down
15 changes: 8 additions & 7 deletions libs/libvtrcapnproto/gen/rr_graph_uxsdcxx.capnp
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Original file line number Diff line number Diff line change
Expand Up @@ -2,11 +2,11 @@
# https://github.com/duck2/uxsdcxx
# Modify only if your build process doesn't involve regenerating this file.
#
# Cmdline: /home/talaeikh/uxsdcxx/uxsdcap.py /home/talaeikh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
# Input file: /home/talaeikh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
# md5sum of input file: 9c14a0ddd3c6bc1e690ca6abf467bae6
# Cmdline: uxsdcxx/uxsdcap.py /home/mohagh18/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
# Input file: /home/mohagh18/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
# md5sum of input file: 65eddcc840064bbb91d7f4cf0b8bf821

@0xa136dd28cdc8783b;
@0xe787bf7696810419;
using Cxx = import "/capnp/c++.capnp";
$Cxx.namespace("ucap");

Expand Down Expand Up @@ -129,9 +129,10 @@ struct SegmentTiming {

struct Segment {
id @0 :Int32;
name @1 :Text;
resType @2 :SegmentResType;
timing @3 :SegmentTiming;
length @1 :Int32;
name @2 :Text;
resType @3 :SegmentResType;
timing @4 :SegmentTiming;
}

struct Segments {
Expand Down

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