[WIP] VIB Upgrades for Tileable Routing Resource Graph on OpenFPGA #2637

tangxifan · 2024-07-02T04:46:16Z

Description

Related Issue

Motivation and Context

How Has This Been Tested?

Types of changes

Bug fix (change which fixes an issue)
New feature (change which adds functionality)
Breaking change (fix or feature that would cause existing functionality to change)

Checklist:

My change requires a change to the documentation
I have updated the documentation accordingly
I have added tests to cover my changes
All new and existing tests passed

Add bend wires

Add vib info

tangxifan

@Wang-Yuanqi-source Please start adding documentation and testcase. We are close to be merged. Most of the codes are clean now. Thank you for the effort!

tangxifan · 2024-11-08T05:17:15Z

vpr/src/tileable_rr_graph/tileable_rr_graph_builder.cpp

                                  device_chan_width,
                                  segment_inf_x, segment_inf_y,
                                  device_grid_annotation,
                                  shrink_boundary,
                                  perimeter_cb,
-                                  through_channel);
+                                  through_channel,
+                                  is_vib_arch);


Since you already pass the vib_grid at LINE168, the flag is_vib_arch is redundant and can be removed here.

tangxifan · 2024-11-08T05:30:02Z

vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp

@@ -103,8 +103,9 @@ void build_rr_graph_edges_for_sink_nodes(const RRGraphView& rr_graph,
 ***********************************************************************/
 void build_rr_graph_edges(const RRGraphView& rr_graph,


Now I understand that the mechanism to build edges for VIB will be very different from the current one. We should create a dedicated function for the VIB, e.g., build_rr_graph_vib_edges(). The current build_rr_graph_edges() will be still there but includes two sub-functions: build_rr_graph_regular_edges() and build_rr_graph_vib_edges().

tangxifan · 2024-11-08T05:31:13Z

vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp

+        for (size_t iy = 0; iy < grids.height(); ++iy) {
+
+            const VibInf* vib = vib_grid.get_vib(layer, ix, iy);
+            if (vib == nullptr) {


Avoid to use any nullptr. Instead, use API like empty() or is_valid()

tangxifan · 2024-11-08T23:00:31Z

vpr/src/tileable_rr_graph/tileable_chan_details_builder.cpp

-            if (0 == itrack % seg_len) {
-                seg_start = true;
+        else{  // bend segment
+            bend_num++;


I understand that you rely on the bend_num find the pairs of bent wires in X- and Y- channel. What if we have different routing channel width in X- and Y- channel ? And we may have different segment distribution in X- and Y- channel. I see the codes here only work in a restricted condition.

Another question is that how are the bent wires impacting the actual routing channel width? When the routing channel width and its wire distribution is defined in the architecture file, are all the bent wires taken into account?

For example, if 4 bent wires are defined in the X-direction channel, should we also define 4 bent wires in the Y-direction channel, in order to match the number?

Or when 4 bent wires are defined in the X-direction channel, the Y-direction channel will automatically include 4 bent wires without any explicit definition in architecture files?

If bent wires are defined in X-direction channel, the same number of bent wires should be defined in Y-direction channel.

O.K. Is there any syntax check or legality checks to ensure this requirement? If not, we should have them somewhere (prefer at parser, if not possible, then in the rr_graph builder)

tangxifan · 2024-11-08T23:28:54Z

vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp

+            }
+
+            size_t count = 0;
+            for (size_t i_first_stage = 0; i_first_stage < vib->get_first_stages().size(); i_first_stage++) {


I remember that you mention that VIB at the right side and top side of the FPGA will have a different arrangement on connectivity. The codes here does not reflect such corner cases. If so, the estimated number of medium numbers will be very different and the pre-allocation on memory could be wrong.

I just modify the coordinates of MEDIUM nodes and edges between nodes in the right side and top side.The number of MEDIUM nodes remains the same.

o.k. it should not impact the total number of nodes then.

tangxifan · 2024-11-08T23:42:25Z

vpr/src/tileable_rr_graph/rr_gsb.h

@@ -186,6 +197,9 @@ class RRGSB {
    void add_opin_node(const RRNodeId& node,
                       const e_side& node_side);

+    /* Add a node to the medium_node_ */
+    void add_medium_node(const RRNodeId& medium_node);


Good effort. Can you also include the MUX name that is defined in your VIB architecture as one of the internal data of GSB? It is debugging and callback. Thanks!

Yes, I will try to add the information of the MUX name.

tangxifan · 2024-11-08T23:52:48Z

vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp

+                    for (size_t i_mux = 0; i_mux < vib_grid.num_medium_nodes(i_layer, ix, iy); i_mux++) {
+                        mux_name_map.emplace(vib_grid.medium_node_name(i_layer, ix, iy, i_mux), i_mux);
+                    }
+                    medium_mux_name2medium_index[i_layer][ix][iy] = mux_name_map;


I believe you should cache the information inside VIB or create a dedicated API in VIB, e.g.,

std::string medium_mux_name_by_index(const size_t& index); size_t medium_mux_index_by_name(const std::string& name);

tangxifan · 2024-11-08T23:58:00Z

vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp

+
+        }
+
+        // process right boundary


I suggest to remove the corner case here. All the I/Os can have their VIB on the top-right corner just like any other tile. This should be the default case.

If any user does not want I/O have their own VIB, they should define it in the VIB arch where they merge the VIB of I/O into adjancent tiles. This should be done through architecture XML, rather than an implicit way

tangxifan · 2024-11-09T00:10:02Z

vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp

+    /* Second stages*/
+    const std::vector<t_second_stage_mux_inf> second_stages = vib->get_second_stages();
+    for (size_t i_second_stage = 0; i_second_stage < second_stages.size(); i_second_stage++) {
+        std::vector<t_from_or_to_inf> froms = second_stages[i_second_stage].froms;


Any difference between the first stage and second stage when checking the nodes and wires? If not, the big content inside the for-loop and be replaced by a common function. What do you think? Bug me if I was wrong.

The checks for the first stage and the second stage are different, because their "from" and "to" node types are different.

O.K. for now. We will refactor this part later.

Wang-Yuanqi-source added 30 commits May 26, 2024 11:15

Update device_grid_annotation.cpp

b49f82f

Update tileable_chan_details_builder.cpp

7cdb3f7

Add bend wires

Update tileable_rr_graph_node_builder.cpp

c8d6be8

Update tileable_rr_graph_gsb.h

f328220

Update tileable_rr_graph_edge_builder.cpp

8a83ee9

Update tileable_rr_graph_gsb.cpp

5e23e1b

Update tileable_rr_graph_gsb.h

063a13d

Update tileable_rr_graph_builder.cpp

48df84d

Update read_xml_arch_file.cpp

9e11eb8

Update physical_types.h

9c6fc7a

Update tileable_chan_details_builder.cpp

b7c24d6

Update chan_node_details.cpp

e9e7bfe

Update chan_node_details.h

260572e

Update tileable_rr_graph_edge_builder.h

ce1b3b4

Update tileable_rr_graph_edge_builder.cpp

dc6aa86

Update tileable_rr_graph_edge_builder.h

6a1f9f8

Update tileable_rr_graph_gsb.h

0d9e9fd

Update rr_graph_view.h

042bef4

Update rr_graph_storage.h

77f802e

Update rr_graph_storage.cpp

ba5cd69

Update rr_graph_builder.h

7ffd299

Update read_xml_arch_file.cpp

155716f

Update physical_types.h

7bd0433

Add vib info

Update read_xml_arch_file.cpp

a0ecbce

Add vib info

Update SetupGrid.cpp

16ab238

Add vib info

Update vpr_context.h

35cccdc

Update SetupGrid.h

7af8feb

Update vpr_api.cpp

56a7e68

Update tileable_rr_graph_edge_builder.cpp

98e7992

Update tileable_rr_graph_builder.cpp

5b32f84

Wang-Yuanqi-source added 9 commits November 4, 2024 10:39

Update rr_graph.xsd

b9d587e

Update tileable_rr_graph_edge_builder.cpp

5ad2329

Update tileable_rr_graph_edge_builder.h

cbcdf0e

Update rr_graph.cpp

84faf43

Update rr_graph_uxsdcxx_serializer.h

4e046ef

Update overuse_report.cpp

60bee8f

Update router_lookahead_map.cpp

0b4cfc2

Update router_lookahead_map_utils.cpp

a182a76

Update rr_gsb.h

6343061

tangxifan commented Nov 9, 2024

View reviewed changes

Wang-Yuanqi-source added 13 commits November 25, 2024 18:48

Update tileable_rr_graph_node_builder.cpp

3bb9068

Update SetupVibGrid.cpp

be709d2

Update tileable_rr_graph_node_builder.h

d7d93c9

Update tileable_rr_graph_builder.cpp

91960e2

Update tileable_rr_graph_edge_builder.cpp

729ae80

Update tileable_rr_graph_gsb.cpp

7a0dfbc

Update rr_gsb.h

2e50bfb

Update tileable_rr_graph_gsb.h

9dac8c4

Update tileable_rr_graph_edge_builder.h

a4479e5

Update vib_inf.h

9ae8a99

Update vib_inf.cpp

230fe0f

Update tileable_rr_graph_gsb.cpp

1678907

Update index.rst

cfe7c2a

github-actions bot added the docs Documentation label Nov 29, 2024

Wang-Yuanqi-source added 4 commits November 29, 2024 10:30

Create VIB.rst

35a82e7

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[WIP] VIB Upgrades for Tileable Routing Resource Graph on OpenFPGA #2637

[WIP] VIB Upgrades for Tileable Routing Resource Graph on OpenFPGA #2637

tangxifan commented Jul 2, 2024 •

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		@@ -103,8 +103,9 @@ void build_rr_graph_edges_for_sink_nodes(const RRGraphView& rr_graph,
		***********************************************************************/
		void build_rr_graph_edges(const RRGraphView& rr_graph,

[WIP] VIB Upgrades for Tileable Routing Resource Graph on OpenFPGA #2637

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[WIP] VIB Upgrades for Tileable Routing Resource Graph on OpenFPGA #2637

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tangxifan commented Jul 2, 2024 • edited Loading

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How Has This Been Tested?

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tangxifan commented Jul 2, 2024 •

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