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Yosys42 #2646

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merged 33 commits into from
Aug 23, 2024
Merged

Yosys42 #2646

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3de7a40
vtr golden result updated
amirarjmand93 Jul 17, 2024
0921f7c
Re-commit changes
amirarjmand93 Jul 20, 2024
1bbe8f7
new golden result
amirarjmand93 Aug 1, 2024
20998f2
new golden result[vtr]
amirarjmand93 Aug 2, 2024
9c0a243
re-generate golden result
amirarjmand93 Aug 2, 2024
99532ca
re-generate two golden result
amirarjmand93 Aug 2, 2024
abbf58d
re-genrate golden result
amirarjmand93 Aug 3, 2024
f1b679b
multless_tasks golden result
amirarjmand93 Aug 3, 2024
4fe2a95
nightly_test 1 is on
amirarjmand93 Aug 3, 2024
b3622fd
regenerate nightly 1 tasks
amirarjmand93 Aug 4, 2024
ef35bd1
fig8+multless
amirarjmand93 Aug 4, 2024
9461ed4
golden result -> multless
amirarjmand93 Aug 4, 2024
9995a61
manual change golden result ->multless
amirarjmand93 Aug 4, 2024
73f0608
golden result changed
amirarjmand93 Aug 5, 2024
6619dc7
task list off
amirarjmand93 Aug 5, 2024
4fd3fdd
figure_8 golden result update
amirarjmand93 Aug 5, 2024
4aff19d
all default tests/tasks -> on
amirarjmand93 Aug 5, 2024
7fc2332
manual change GR
amirarjmand93 Aug 5, 2024
c7d3487
pass_requirements update
amirarjmand93 Aug 5, 2024
7b44ebe
pass_requirments update + tests off
amirarjmand93 Aug 5, 2024
365bbd6
Tests on
amirarjmand93 Aug 5, 2024
8d565a0
edit typo
amirarjmand93 Aug 5, 2024
4198034
disable mvml.v and Lup32peeng.v from vtr_reg_nightly_test3/vtr_reg_qo…
amirarjmand93 Aug 20, 2024
fb168b5
disable mcml.v and LU32PEEng.v in predictor_off test
amirarjmand93 Aug 20, 2024
9046d9d
update golden
amirarjmand93 Aug 21, 2024
fdbb03c
update figure 8
amirarjmand93 Aug 21, 2024
5768d9d
update golden result
amirarjmand93 Aug 21, 2024
0a0f5c8
update golden result
amirarjmand93 Aug 21, 2024
4a759ab
Absolute Threshold ++
amirarjmand93 Aug 21, 2024
90d99e8
Absolute Threshold ++
amirarjmand93 Aug 22, 2024
307dc9c
update lower band min_chan_width_route_time
amirarjmand93 Aug 22, 2024
71ffc6f
[Yosys] Cleaned Up Some Small Issues
AlexandreSinger Aug 23, 2024
78352e7
Merge remote-tracking branch 'origin/master' into Yosys42
AlexandreSinger Aug 23, 2024
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4 changes: 2 additions & 2 deletions .github/workflows/nightly_test.yml
Original file line number Diff line number Diff line change
Expand Up @@ -62,9 +62,9 @@ jobs:
- {test: "vtr_reg_strong", cores: "16", options: "", cmake: "-DVTR_ASSERT_LEVEL=3", extra_pkgs: "libeigen3-dev"}
- {test: "vtr_reg_strong_odin", cores: "16", options: "", cmake: "-DVTR_ASSERT_LEVEL=3 -DWITH_ODIN=ON", extra_pkgs: "libeigen3-dev"}
- {test: "vtr_reg_strong_odin", cores: "16", options: "-skip_qor", cmake: "-DVTR_ASSERT_LEVEL=3 -DVTR_ENABLE_SANITIZE=ON -DWITH_ODIN=ON", extra_pkgs: "libeigen3-dev"}
- {test: "vtr_reg_system_verilog", cores: "16", options: "", cmake: "-DYOSYS_F4PGA_PLUGINS=ON", extra_pkgs: ""}
# - {test: "vtr_reg_system_verilog", cores: "16", options: "", cmake: "-DYOSYS_F4PGA_PLUGINS=ON", extra_pkgs: ""} # Test turned off -> F4PGA conflicts with Yosys (version 42)
- {test: "odin_reg_strong", cores: "16", options: "", cmake: "-DWITH_ODIN=ON", extra_pkgs: ""}
- {test: "parmys_reg_strong", cores: "16", options: "", cmake: "-DYOSYS_F4PGA_PLUGINS=ON", extra_pkgs: ""}
- {test: "parmys_reg_strong", cores: "16", options: "", cmake: "-DYOSYS_F4PGA_PLUGINS=OFF", extra_pkgs: ""}

env:
DEBIAN_FRONTEND: "noninteractive"
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -2,5 +2,5 @@ regression_test/benchmark/task/koios/koios_large
regression_test/benchmark/task/koios/koios_large_no_hb
regression_test/benchmark/task/koios/koios_proxy
regression_test/benchmark/task/koios/koios_proxy_no_hb
regression_test/benchmark/task/koios/koios_sv
regression_test/benchmark/task/koios/koios_sv_no_hb
#regression_test/benchmark/task/koios/koios_sv
#regression_test/benchmark/task/koios/koios_sv_no_hb
Original file line number Diff line number Diff line change
Expand Up @@ -479,20 +479,20 @@
"Multiplier": 1,
"Memory": 8,
"generic logic size": 4,
"Longest Path": 269,
"Longest Path": 274,
"Average Path": 3,
"Estimated LUTs": 4797,
"Estimated LUTs": 4777,
"Total Node": 1957,
"Wires": 5595,
"Wire Bits": 10315,
"Wires": 5591,
"Wire Bits": 10025,
"Public Wires": 240,
"Public Wire Bits": 240,
"Total Cells": 8221,
"MUX": 2180,
"Total Cells": 8185,
"MUX": 2164,
"XOR": 40,
"OR": 2850,
"AND": 1455,
"NOT": 639,
"OR": 2836,
"AND": 1451,
"NOT": 637,
"DFFs": [
"$_DFF_P_ 645"
],
Expand Down Expand Up @@ -533,8 +533,8 @@
"Average Path": 3,
"Estimated LUTs": 41888,
"Total Node": 5344,
"Wires": 9772,
"Wire Bits": 102222,
"Wires": 9777,
"Wire Bits": 102242,
"Public Wires": 391,
"Public Wire Bits": 391,
"Total Cells": 31999,
Expand Down Expand Up @@ -585,8 +585,8 @@
"Average Path": 3,
"Estimated LUTs": 42386,
"Total Node": 5593,
"Wires": 10802,
"Wire Bits": 103242,
"Wires": 10796,
"Wire Bits": 103210,
"Public Wires": 648,
"Public Wire Bits": 648,
"Total Cells": 32995,
Expand Down Expand Up @@ -840,16 +840,16 @@
"Average Path": 4,
"Estimated LUTs": 4564,
"Total Node": 2961,
"Wires": 6943,
"Wire Bits": 11526,
"Wires": 6934,
"Wire Bits": 11506,
"Public Wires": 501,
"Public Wire Bits": 501,
"Total Cells": 8995,
"Total Cells": 8955,
"MUX": 2605,
"XOR": 311,
"OR": 1858,
"AND": 1687,
"NOT": 711,
"OR": 1861,
"AND": 1683,
"NOT": 672,
"DFFs": [
"$_DFF_P_ 1312"
],
Expand All @@ -861,9 +861,6 @@
"test_name": "freecores/mips_16/k6_frac_N10_frac_chain_mem32K_40nm",
"architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
"warnings": [
"mips_16.v:0 System task `$display' outside initial block is unsupported.",
"mips_16.v:0 System task `$display' outside initial block is unsupported.",
"mips_16.v:0 System task `$display' outside initial block is unsupported.",
"Replacing memory \\reg_array with list of registers. See ../vtr_flow/benchmarks//freecores/mips_16.v:791",
"Ignoring module EX_stage because it contains processes (run 'proc' command first).",
"Ignoring module data_mem because it contains processes (run 'proc' command first).",
Expand Down
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