Fix clang format not working in CI

.clang-format

@@ -11,7 +11,7 @@ AllowAllParametersOfDeclarationOnNextLine: false
 AllowShortBlocksOnASingleLine: true
 AllowShortCaseLabelsOnASingleLine: false
 AllowShortFunctionsOnASingleLine: true
-AllowShortIfStatementsOnASingleLine: true
+AllowShortIfStatementsOnASingleLine: false
 AllowShortLoopsOnASingleLine: false
 AlwaysBreakAfterDefinitionReturnType: None
 AlwaysBreakAfterReturnType: None
@@ -42,7 +42,7 @@ BreakConstructorInitializersBeforeComma: false
 BreakConstructorInitializers: BeforeComma
 BreakAfterJavaFieldAnnotations: false
 BreakStringLiterals: true
-ColumnLimit: 0
+ColumnLimit: 120
 CommentPragmas:  '^ IWYU pragma:'
 CompactNamespaces: false
 ConstructorInitializerAllOnOneLineOrOnePerLine: false
@@ -68,7 +68,7 @@ IncludeIsMainRegex: '([-_](test|unittest))?$'
 IndentCaseLabels: true
 IndentWidth:     4
 IndentWrappedFunctionNames: false
-IndentPPDirectives: AfterHash
+IndentPPDirectives: None
 JavaScriptQuotes: Leave
 JavaScriptWrapImports: true
 KeepEmptyLinesAtTheStartOfBlocks: false

.github/workflows/test.yml

@@ -87,6 +87,8 @@ jobs:
       with:
         python-version: 3.10.10
     - uses: actions/checkout@v4
+      with:
+        submodules: 'true'
 
     - name: Install dependencies
       run: ./.github/scripts/install_dependencies.sh

libs/libarchfpga/src/arch_check.h

@@ -56,7 +56,9 @@ void warn_model_missing_timing(const t_model* model, const char* file, uint32_t
  * @param sub_tile sub tile to check
  * @param logical_block logical block type
  */
-void check_port_direct_mappings(t_physical_tile_type_ptr physical_tile, t_sub_tile* sub_tile, t_logical_block_type_ptr logical_block);
+void check_port_direct_mappings(t_physical_tile_type_ptr physical_tile,
+                                t_sub_tile* sub_tile,
+                                t_logical_block_type_ptr logical_block);
 
 /**
  * @brief Checks the timing consistency between tha pb_type and the corresponding model.

libs/libarchfpga/src/arch_util.h

@@ -74,9 +74,7 @@ t_logical_block_type get_empty_logical_type(const char* name = EMPTY_BLOCK_NAME)
 
 std::unordered_set<t_logical_block_type_ptr> get_equivalent_sites_set(t_physical_tile_type_ptr type);
 
-void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type,
-                                              char* new_name,
-                                              t_pb_type* copy);
+void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type, char* new_name, t_pb_type* copy);
 
 void ProcessLutClass(t_pb_type* lut_pb_type);
 
@@ -86,14 +84,11 @@ e_power_estimation_method power_method_inherited(e_power_estimation_method paren
 
 void CreateModelLibrary(t_arch* arch);
 
-void SyncModelsPbTypes(t_arch* arch,
-                       const std::vector<t_logical_block_type>& Types);
+void SyncModelsPbTypes(t_arch* arch, const std::vector<t_logical_block_type>& Types);
 
-void SyncModelsPbTypes_rec(t_arch* arch,
-                           t_pb_type* pb_type);
+void SyncModelsPbTypes_rec(t_arch* arch, t_pb_type* pb_type);
 
-void primitives_annotation_clock_match(t_pin_to_pin_annotation* annotation,
-                                       t_pb_type* parent_pb_type);
+void primitives_annotation_clock_match(t_pin_to_pin_annotation* annotation, t_pb_type* parent_pb_type);
 
 bool segment_exists(const t_arch* arch, std::string name);
 const t_segment_inf* find_segment(const t_arch* arch, std::string name);
@@ -106,8 +101,12 @@ bool block_type_contains_blif_model(t_logical_block_type_ptr type, const std::st
 //Returns true of a pb_type (or it's children) contain the specified blif model name
 bool pb_type_contains_blif_model(const t_pb_type* pb_type, const std::string& blif_model_name);
 
-const t_pin_to_pin_annotation* find_sequential_annotation(const t_pb_type* pb_type, const t_model_ports* port, enum e_pin_to_pin_delay_annotations annot_type);
-const t_pin_to_pin_annotation* find_combinational_annotation(const t_pb_type* pb_type, std::string in_port, std::string out_port);
+const t_pin_to_pin_annotation* find_sequential_annotation(const t_pb_type* pb_type,
+                                                          const t_model_ports* port,
+                                                          enum e_pin_to_pin_delay_annotations annot_type);
+const t_pin_to_pin_annotation* find_combinational_annotation(const t_pb_type* pb_type,
+                                                             std::string in_port,
+                                                             std::string out_port);
 
 /**
  * @brief Updates the physical and logical types based on the equivalence between one and the other.

libs/libarchfpga/src/cad_types.h

@@ -120,9 +120,7 @@ struct t_pack_patterns {
  * Linked list for easy insertion/deletion
  */
 struct t_cluster_placement_primitive {
-    t_cluster_placement_primitive() {
-        pb_graph_node = nullptr;
-    }
+    t_cluster_placement_primitive() { pb_graph_node = nullptr; }
     t_pb_graph_node* pb_graph_node;
     bool valid;
     float base_cost;        /* cost independent of current status of packing */

libs/libarchfpga/src/clock_types.h

@@ -4,11 +4,7 @@
 #include <string>
 #include <vector>
 
-enum class e_clock_type {
-    SPINE,
-    RIB,
-    H_TREE
-};
+enum class e_clock_type { SPINE, RIB, H_TREE };
 
 struct t_metal_layer {
     float r_metal;

libs/libarchfpga/src/device_grid.h

@@ -25,24 +25,22 @@ class DeviceGrid {
   public:
     DeviceGrid() = default;
     DeviceGrid(std::string grid_name, vtr::NdMatrix<t_grid_tile, 3> grid);
-    DeviceGrid(std::string grid_name, vtr::NdMatrix<t_grid_tile, 3> grid, std::vector<t_logical_block_type_ptr> limiting_res);
+    DeviceGrid(std::string grid_name,
+               vtr::NdMatrix<t_grid_tile, 3> grid,
+               std::vector<t_logical_block_type_ptr> limiting_res);
 
     const std::string& name() const { return name_; }
 
     ///@brief Return the number of layers(number of dies)
-    inline int get_num_layers() const {
-        return (int)grid_.dim_size(0);
-    }
+    inline int get_num_layers() const { return (int)grid_.dim_size(0); }
 
     ///@brief Return the width of the grid at the specified layer
     size_t width() const { return grid_.dim_size(1); }
     ///@brief Return the height of the grid at the specified layer
     size_t height() const { return grid_.dim_size(2); }
 
     ///@brief Return the size of the flattened grid on the given layer
-    inline size_t grid_size() const {
-        return grid_.size();
-    }
+    inline size_t grid_size() const { return grid_.size(); }
 
     ///@brief deallocate members of DeviceGrid
     void clear();
@@ -114,9 +112,7 @@ class DeviceGrid {
     }
 
     ///@brief Return the nth t_grid_tile on the given layer of the flattened grid - Used by serializer functions
-    inline const t_grid_tile* get_grid_locs_grid_loc(int n) const {
-        return &grid_.get(n);
-    }
+    inline const t_grid_tile* get_grid_locs_grid_loc(int n) const { return &grid_.get(n); }
 
   private:
     ///@brief count_instances() counts the number of each tile type on each layer and store it in instance_counts_. It is called in the constructor.
@@ -131,7 +127,8 @@ class DeviceGrid {
      * @note which can be used for indexing in the second dimension, allowing
      * @note traditional 2-d indexing to be used
      */
-    vtr::NdMatrix<t_grid_tile, 3> grid_; //This stores the grid of complex blocks. It is a 3D matrix: [0..num_layers-1][0..grid.width()-1][0..grid_height()-1]
+    vtr::NdMatrix<t_grid_tile, 3>
+        grid_; //This stores the grid of complex blocks. It is a 3D matrix: [0..num_layers-1][0..grid.width()-1][0..grid_height()-1]
 
     ///@brief instance_counts_ stores the number of each tile type on each layer. It is initialized in count_instances().
     std::vector<std::map<t_physical_tile_type_ptr, size_t>> instance_counts_; /* [layer_num][physical_tile_type_ptr] */