Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

[AP] Global Placer #2806

Conversation

AlexandreSinger
Copy link
Contributor

Created the Global Placer base class which will create a partial placement based on the netlist and the architecture. This attempts to find a "globally" good placement, without considering all of the complex constraints of the FPGA architecture (without clustering).

Implemented a SimPL-based Global Placer which maintains an upper and lower bound solution which slowly approach each other over several iterations. The lower-bound is the analytically solved solution which tries to optimize the placement (hinted by the upper bound solution). The upper-bound solution is the lower-bound solution which has been partially legalized.

@github-actions github-actions bot added VPR VPR FPGA Placement & Routing Tool lang-cpp C/C++ code labels Nov 12, 2024
@AlexandreSinger
Copy link
Contributor Author

@vaughnbetz This has passed CI. Please review. This is a much smaller PR than the last one. It adds the Global Placer class into the AP flow which handles how the Analytical Solver interacts with the Partial Legalizer.

vpr/src/analytical_place/global_placer.h Outdated Show resolved Hide resolved
vpr/src/analytical_place/global_placer.h Show resolved Hide resolved
vpr/src/analytical_place/global_placer.h Outdated Show resolved Hide resolved
vpr/src/analytical_place/global_placer.cpp Outdated Show resolved Hide resolved
vpr/src/analytical_place/global_placer.cpp Outdated Show resolved Hide resolved
@AlexandreSinger
Copy link
Contributor Author

@vaughnbetz Thank you for the review. I have resolved your comments. I agree that using an absolute gap was not a sustainable idea. I changed it to a percent gap, as you suggested, where the percent gap is equal to (UB - LB) / UB [since UB should be larger than LB). I set the target percent gap to 10%, which seems to work relatively well for some of the smaller circuits I test on. In the future I will tune this to a better value. Let me know if you have any further comments or if we can merge this.

@vaughnb-cerebras
Copy link

Great, thanks.

Copy link

@vaughnb-cerebras vaughnb-cerebras left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Looks good, but one last change: we should call it relative gap instead of percent gap.

vpr/src/analytical_place/global_placer.h Outdated Show resolved Hide resolved
Created the Global Placer base class which will create a partial
placement based on the netlist and the architecture. This attempts to
find a "globally" good placement, without considering all of the complex
constraints of the FPGA architecture (without clustering).

Implemented a SimPL-based Global Placer which maintains an upper and
lower bound solution which slowly approach each other over several
iterations. The lower-bound is the analytically solved solution which
tries to optimize the placement (hinted by the upper bound solution).
The upper-bound solution is the lower-bound solution which has been
partially legalized.
@AlexandreSinger
Copy link
Contributor Author

@vaughnbetz Completely agree. I like that way better than percent! I have updated the code and documentation. Shall we merge?

@vaughnbetz vaughnbetz merged commit 2586a98 into verilog-to-routing:master Nov 14, 2024
37 checks passed
@vaughnbetz
Copy link
Contributor

Done!

@AlexandreSinger AlexandreSinger deleted the feature-ap-global-placement branch November 27, 2024 19:23
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
lang-cpp C/C++ code VPR VPR FPGA Placement & Routing Tool
Projects
None yet
Development

Successfully merging this pull request may close these issues.

3 participants