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Created the Global Placer base class which will create a partial placement based on the netlist and the architecture. This attempts to find a "globally" good placement, without considering all of the complex constraints of the FPGA architecture (without clustering).

Implemented a SimPL-based Global Placer which maintains an upper and lower bound solution which slowly approach each other over several iterations. The lower-bound is the analytically solved solution which tries to optimize the placement (hinted by the upper bound solution). The upper-bound solution is the lower-bound solution which has been partially legalized.

@github-actions github-actions bot added VPR VPR FPGA Placement & Routing Tool lang-cpp C/C++ code labels Nov 12, 2024
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@vaughnbetz This has passed CI. Please review. This is a much smaller PR than the last one. It adds the Global Placer class into the AP flow which handles how the Analytical Solver interacts with the Partial Legalizer.

@AlexandreSinger AlexandreSinger force-pushed the feature-ap-global-placement branch from c45d0b4 to dea8847 Compare November 13, 2024 21:39
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@vaughnbetz Thank you for the review. I have resolved your comments. I agree that using an absolute gap was not a sustainable idea. I changed it to a percent gap, as you suggested, where the percent gap is equal to (UB - LB) / UB [since UB should be larger than LB). I set the target percent gap to 10%, which seems to work relatively well for some of the smaller circuits I test on. In the future I will tune this to a better value. Let me know if you have any further comments or if we can merge this.

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Great, thanks.

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Looks good, but one last change: we should call it relative gap instead of percent gap.

Created the Global Placer base class which will create a partial
placement based on the netlist and the architecture. This attempts to
find a "globally" good placement, without considering all of the complex
constraints of the FPGA architecture (without clustering).

Implemented a SimPL-based Global Placer which maintains an upper and
lower bound solution which slowly approach each other over several
iterations. The lower-bound is the analytically solved solution which
tries to optimize the placement (hinted by the upper bound solution).
The upper-bound solution is the lower-bound solution which has been
partially legalized.
@AlexandreSinger AlexandreSinger force-pushed the feature-ap-global-placement branch from dea8847 to fe92b3e Compare November 13, 2024 23:57
@AlexandreSinger
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@vaughnbetz Completely agree. I like that way better than percent! I have updated the code and documentation. Shall we merge?

@vaughnbetz vaughnbetz merged commit 2586a98 into verilog-to-routing:master Nov 14, 2024
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Done!

@AlexandreSinger AlexandreSinger deleted the feature-ap-global-placement branch November 27, 2024 19:23
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3 participants