Add blueprint for cahp-pearl

share/cahp-pearl.toml

@@ -0,0 +1,46 @@
+[[file]]
+type = "iyokanl1-json"
+path = "pearl-core.json"
+name = "core"
+
+[[builtin]]
+type = "rom"
+name = "rom"
+in_addr_width = 7
+out_rdata_width = 32
+
+[[builtin]]
+type = "ram"
+name = "ram"
+in_addr_width = 8
+in_wdata_width = 16
+out_rdata_width = 16
+
+[connect]
+"rom/addr[0:6]"          = "core/io_rom_addr[0:6]"
+"core/io_rom_data[0:31]" = "rom/rdata[0:31]"
+
+"ram/wren"      = "core/io_ram_writeEnable"
+"ram/addr[0:7]" = "core/io_ram_addr[0:7]"
+"ram/wdata[0:15]" = "core/io_ram_writeData[0:15]"
+"core/io_ram_readData[0:15]" = "ram/rdata[0:15]"
+
+"core/reset" = "@reset"
+"@finflag" = "core/io_finishFlag"
+
+"@reg_x0[0:15]" = "core/io_mainRegOut_x0[0:15]"
+"@reg_x1[0:15]" = "core/io_mainRegOut_x1[0:15]"
+"@reg_x2[0:15]" = "core/io_mainRegOut_x2[0:15]"
+"@reg_x3[0:15]" = "core/io_mainRegOut_x3[0:15]"
+"@reg_x4[0:15]" = "core/io_mainRegOut_x4[0:15]"
+"@reg_x5[0:15]" = "core/io_mainRegOut_x5[0:15]"
+"@reg_x6[0:15]" = "core/io_mainRegOut_x6[0:15]"
+"@reg_x7[0:15]" = "core/io_mainRegOut_x7[0:15]"
+"@reg_x8[0:15]" = "core/io_mainRegOut_x8[0:15]"
+"@reg_x9[0:15]" = "core/io_mainRegOut_x9[0:15]"
+"@reg_x10[0:15]" = "core/io_mainRegOut_x10[0:15]"
+"@reg_x11[0:15]" = "core/io_mainRegOut_x11[0:15]"
+"@reg_x12[0:15]" = "core/io_mainRegOut_x12[0:15]"
+"@reg_x13[0:15]" = "core/io_mainRegOut_x13[0:15]"
+"@reg_x14[0:15]" = "core/io_mainRegOut_x14[0:15]"
+"@reg_x15[0:15]" = "core/io_mainRegOut_x15[0:15]"