🧩 Starter template for ASIC hardware IP blocks with Vyges metadata, OpenLane integration, and comprehensive documentation

📋 Vyges Metadata Specification - Standardized format for hardware IP discovery and integration

A hardware implementation of Meta's MLow audio codec, delivering 2x better quality than Opus at 6kbps while maintaining 10% lower computational complexity. Optimized for RTC applications on resource-constrained devices.

SPI master controller with APB interface, multi-mode support (all SPI modes), configurable FIFO, and interrupt features for ASIC/FPGA integration.

Configurable, high-performance FFT hardware IP core for ASIC/FPGA. Pipelined radix-2 DIF, 256–4096-point support, 16-bit fixed-point, double-buffered memory, APB/AXI interfaces. Optimized for throughput and low latency.

A configurable UART controller IP with APB interface, FIFO support, and interrupt capabilities. Designed for SkyWater 130nm Open Source PDK with comprehensive verification and OpenLane integration.

Configurable PWM controller with multiple channels and precise frequency control

Programmable ADC IP with Cadence PDK support, featuring behavioral models, comprehensive testbenches, and automated verification flows for mixed-signal design.

Lyra Codec - VQDQ